Resistive switching characteristics of Si3N4-based resistive-switching random-access memory cell with tunnel barrier for high density integration and low-power applications

Abstract

In this letter, a bipolar resistive-switching random-access memory (RRAM) in Ni/Si3N4/SiO2/p+-Si structure and its fabrication process are demonstrated. The proposed device with double-layer dielectrics consisting of Si3N4 layer (5 nm) as a resistive switching and SiO2 (2.5 nm) layer for the tunnel barrier is investigated in comparison with that having a single layer of Si3N4. Double-layer cell shows ultra-low power operation under a compliance current (ICOMP) of 500 nA, which ensures the reset current (IRESET) of sub-1 μA much lower than that of the single-layer cell. Also, large on/off ratio (∼105) has been obtained since the SiO2 layer efficiently suppresses the current in the high-resistance state. Moreover, maximum selectivity in double-layer cell is 122 when 1/2 read bias scheme is applied to the crossbar array. Highly nonlinear I-V characteristics of the double-layer Si3N4-based RRAM cell warrant the realization of selector-free RRAM cell in the crossbar array pursuing higher integration density.

Memristor with Ag‐Cluster‐Doped TiO2 Films as Artificial Synapse for Neuroinspired Computing

“…Fitting results of Ag/pureTiO 2 /Pt show that the charge transport behavior is consistent with a classical trap-controlled space charge limited conduction (SCLC), which consists of three portions: the Ohmic region (I/V), the Child's law region (I/V 2 ), and the steep current increase region, as shown in Figure 3d. [31] However, the I-V curve of Ag/TiO 2 :Ag/Pt devices as shown in Figure 3a was fitted as ln(I/V 2 ) versus 1/V of the I-V regions data at HRS, [32][33][34] as shown in Figure 3(c). The fitting results show linear behaviors and can be divided into two parts in the graphs, meaning that the conduction behaviors are well described by the F-N tunneling conduction model and directly tunneling.…”

Fully Si compatible SiN resistive switching memory with large self-rectification ratio

“…[9][10][11][12][13][14][15] Among them, Si 3 N 4 is considered one of the most interesting resistive-switching materials thanks to its abundant defects, which play an important role in resistive switching. [16][17][18][19][20][21][22][23][24] Furthermore, Si 3 N 4 -based RRAM has numerous merits of fast switching speed, low switching current, strong endurance, good retention, full compatibility to conventional Si CMOS processing, and capability of both unipolar and bipolar switching modes. [16][17][18][19][20][21][22] For realization of the high-density crossbar array configuration, sneak current which leads to read-out errors should be suppressed.…”

“…[16][17][18][19][20][21][22][23][24] Furthermore, Si 3 N 4 -based RRAM has numerous merits of fast switching speed, low switching current, strong endurance, good retention, full compatibility to conventional Si CMOS processing, and capability of both unipolar and bipolar switching modes. [16][17][18][19][20][21][22] For realization of the high-density crossbar array configuration, sneak current which leads to read-out errors should be suppressed. 25 In order to resolve the problem of sneak current, linkage of the individual memory cell and a nonlinear access device is required.…”

“…Si pathways can be formed and broken by controlling the applied electric field across the Si 3 N 4 layer for low-resistance state (LRS) and high-resistance state (HRS), respectively. [16][17][18][19][20][21][22][23][24] For unipolar resistive switching, the bias is swept keeping the same polarity in the negative region. The electroforming step (the first set process) is required with compliance current (I COMP ) to switch the RRAM cell from the initial state to the LRS.…”

“…14 We have focused on developing RRAM cells in the MIS structure which has a number of advantages over the conventional metal-insulator-metal (MIM) structure. [16][17][18][19] In the MIS structure, the Si bottom electrode (BE) can be easily integrated through CMOS technology without complicating the backend-of-the-line (BEOL) [29][30][31][32][33][34] and has higher flexibility in physical design of RRAM devices by using an anisotropic wet etching process. 35,36 In this work, the resistive switching characteristics of RRAM devices in the MIS structure are studied considering the effects of doping concentration in the Si BE, which has been seldom reported yet.…”