Resistor-logic demultiplexers for nanoelectronics based on constant-weight codes

Abstract

The voltage margin of a resistor-logic demultiplexer can be improved significantly by basing its connection pattern on a constant-weight code. Each distinct code determines a unique demultiplexer, and therefore a large family of circuits is defined. We consider using these demultiplexers for building nanoscale crossbar memories, and determine the voltage margin of the memory system based on a particular code. We determine a purely code-theoretic criterion for selecting codes that will yield memories with large voltage margins, which is to minimize the ratio of the maximum to the minimum Hamming distance between distinct codewords. For the specific example of a 64 × 64 crossbar, we discuss what codes provide optimal performance for a memory.

Nanoelectronics from the bottom up

“…Furthermore, linear resistor logic suffers from limited voltage margin: the voltage difference between the selected and non-selected nanowires may not be large enough to complete the specific write/erase function. To improve the voltage margin, several techniques have been proposed using CMOS coding to eliminate the worst-case scenarios 41,55 . However, considering the limited geometry and functions available in the crossbar resistorlogic, it is reasonable to expect workable demuxes to be in the form of hybrid resistor-crossbar/transistor structures in which the transistor circuitry provides the more difficult functions such as signal gain, restoration, inversion and impedance matching.…”

Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits

“…Several possible solutions have been proposed to tackle this challenge, which may be categorized based on whether the microwire-to-nanowire accessibility is realized through direct mircowire-nanowire ohmic contact [9,11] or a logic circuit called microwire-to-nanowire demultiplexer (demux) [12][13][14][15][16]. All the proposed demux design solutions have a crossbar structure consisting of one layer of parallel nanowires and one layer of parallel microwires.…”

“…In prior work on demux design, the demultiplexing function is realized by implementing a single type of devices such as resistor [16], diode [12], or field effect transistor (FET) [13][14][15] at a subset of the microwire-nanowire crosspoints. Because the nonlinear nature of diode's and FET's electrical characteristics can well match the nonlinear nature of the desired demultiplexing function, diode-logic and FET-logic demuxes can, in principle, very well approximate the ideal demultiplexing behavior.…”

“…Because the nonlinear nature of diode's and FET's electrical characteristics can well match the nonlinear nature of the desired demultiplexing function, diode-logic and FET-logic demuxes can, in principle, very well approximate the ideal demultiplexing behavior. However, as pointed out in [16,17], diode-logic and FET-logic demuxes suffer from significant difficulties of reliable fabrication using current technology. Moreover, FET-logic demuxes tend to suffer from low operational speed because of the serial chains of FETs along the signal path.…”

“…Nevertheless, due to the linear nature of resistor's electrical characteristics, resistor-logic demux inherently cannot well approximate the desired nonlinear demultiplexing behavior. Recent work [16,17] has applied constant weight codes, a topic in classical coding theory to design resistor-logic demux structure with optimal operation margin, which may relatively better approximate the demultiplexing behavior.…”