Resource-constrained scheduling of partitioned algorithms on processor arrays

Dion, Michèle; Risset, Tanguy; Robert, Yves

doi:10.1016/0167-9260(95)00022-4

Cited by 10 publications

(10 citation statements)

References 9 publications

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“…It may be noted that the system of equations (11) can be written in the form (8) . à In a special case (when the vector of external variables is not taken into account), Theorem 1 is proved in [26].…”

Section: Functions Using Arrays At Iterations Of Loop Nestsmentioning

confidence: 99%

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Parallelization of sequential programs: distribution of arrays among processors and structurization of communications

Adutskevich

Likhoded

Sikorsky³

2012

Cybern Syst Anal

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Section: Functions Using Arrays At Iterations Of Loop Nestsmentioning

confidence: 99%

“…Another approach lies in obtaining block versions of an algorithm, i.e., partitioning the iteration space of loop nests in a special way [1, [10][11][12][13]. The objective of such a partitioning is the increase in the size of packages of transferred data and decrease in the frequency of communications.…”

Section: Introductionmentioning

confidence: 99%

Parallelization of sequential programs: distribution of arrays among processors and structurization of communications

Adutskevich

Likhoded

Sikorsky³

2012

Cybern Syst Anal

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“…Functions of the type (3)-(5) form a basic tool of investigations in methods of static parallelization of programs [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18].…”

Section: Statement Of the Problemmentioning

confidence: 99%

Optimization of data exchange in parallel computers with distributed memory

Adutskevich

Likhoded

2006

Cybern Syst Anal

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The problem of optimization of communications during the execution of a program on a parallel computer with distributed memory is investigated. Statements are formulated that make it possible to determine the possibility of organization of data broadcast and translation. The conditions proposed are represented in the form suitable for practical application and can be used for automated parallelization of programs.Keywords: parallel computations, parallelization of algorithms, affine cycle nests, parallel computer with distributed memory, optimization of communications.To map algorithms represented by sequential programs onto parallel computers with distributed memory, operations and data of an algorithm should be distributed between processors and also the order of execution of operations and data exchanges should be determined. During the execution of algorithms, such computers expend a considerable amount of time for communications (data exchange) between processors. Therefore, the distribution of operations and data between processors should be realized so that the number and amount of communications are decreased (the problem of aligned distribution of operations and data over processors); moreover, the communication structure should be optimized.Many investigations are devoted to the problem of decreasing communication expenditures. Let us give a brief review. An approach consists of partitioning algorithms into blocks of independent computations [1][2][3][4][5]. Note that, in practice, an algorithm can rarely be decomposed into independent components. Another approach (used in practice) lies in obtaining block versions of an algorithm and a special partition of the space of iterations of cycle nests (nested loops) [1, 6-10]. This approach is directed toward the minimization of overheads for data exchanges and does not touch on the problem of distribution of data arrays.One more approach consists of searching for the initial (before the moment of execution of a program) distribution of operations and data over processors that minimizes possible data exchanges during the execution of the program. Aspects of this problem are considered in [11][12][13][14][15] in which the problems of minimization of the number of nonlocal communications, optimization of location modes of data arrays, aligned data distribution, obtaining of conveyor parallelism, and improvement of the locality of cycle nests are investigated.There exists an approach in which a decrease in communication expenditures is obtained owing to the determination of a scheme of data transmission from one processor to another [16] rather than by the choice of an optimal distribution of initial data.The idea of obtaining of an initial joint data distribution and the subsequent mode of data exchange is realized (without explicit specification of the distribution) in [17] for algorithms specified by affine recurrent equations. Of interest are the adaptation of this approach to algorithms specified by cycle nests, investigation of the possibility of applicati...

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Section: : Introductionmentioning

confidence: 99%

“…However, as mentioned in [6], the ILP formulation as described in [2] can only be used in a very restrictive instance of the scheduling problem. In [6], the ILP-model proposed in [18] has been extended to include communication delays and communication constraints. Unfortunately, the size of this model (measured in the number of integer variables) is proportional to the number of points inside a tile which is executed sequentially by one processing element and all processing elements are equal.…”

Section: : Introductionmentioning

confidence: 99%

Scheduling of partitioned regular algorithms on processor arrays with constrained resources

Teich

Thiele

Zhang

Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96

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A single integer h e a r programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of uvailable processors and communication capabilities are taken into account, but also processor caches and constraints on the size of available memories are modeled and taken into account in the optimization model. 2) Diferent types of processors can be handled.3) The size of the optimization model (number of integer variables) is independent of the size of ihe tiles to be executed. Hence, 4) the number of integer variables in the optimization moder' is greatly reduced suchthat problems of relevant size can be solved in practical execution time. 1: IntroductionThis paper deals with techniques for mapping partitioned regular algorithms onto massively parallel processor arrays that are realized in VLSI.The most important problems to be solved in the synthesis process include scheduling where the operations in the algorithmic description are mapped onto discrete time steps, and binding where the operations and variables in the algorithmic description are mapped onto shared hardware resources.Partitioning methods have been proposed for mapping an arbitrary size regular algorithm onto a processor array with a restricted number of processing elcments and dimension. The aim is to establish a balance between local memory, I/O-rate and computation rate, see e.g., [20, 151. However, while the emphasis of partitioning has generally been on restricted resources on the array level (i.e., number of processing elements) (regular resource constraints), typical problems like a constrained number of functional resources, communication resources and memory resources inside the processing elements (so called irregukrr refource constraints) have been ignored. For example, the number of available function units in a processing element is not sufficient to execute the operations assigned to them concurrently.As a result, a new research direction on extending array mapping methodologies can be recognized in the fusion of mapping techniques for regular processor arrays and high-level synthesis tasks, see, e.g., [20, 4, 2, 18, 6, 51. Here is a short overview of recent work in this direction:Except of special cases, resource constrained scheduling problems are known to he NPcomplete, see e.g., [3, 71. Hence, numerous heuristic methods have been proposed in order to

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Resource-constrained scheduling of partitioned algorithms on processor arrays

Cited by 10 publications

References 9 publications

Parallelization of sequential programs: distribution of arrays among processors and structurization of communications

Parallelization of sequential programs: distribution of arrays among processors and structurization of communications

Optimization of data exchange in parallel computers with distributed memory

Scheduling of partitioned regular algorithms on processor arrays with constrained resources

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