Retiming and recycling for elastic systems with early evaluation

Bufistov, Dmitry; Cortadella, Jordi; Galceran-Oms, Marc; Júlvez, Jorge; Kishinevsky, Michael

doi:10.1145/1629911.1629988

Cited by 8 publications

(7 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Then, the new EB can be retimed backwards across the node with delay 8, and the bubble between nodes 8 and 9 can be removed. This new configuration has a cycle time of 11 units, but the estimated throughput using an ILP model [7] is higher, 0.918, since there is only one cycle with a bubble 2 compared to Fig. 16(a), where two of the three cycles have bubbles.…”

Section: Re-designing For Average Performancementioning

confidence: 94%

“…The retiming and recycling optimizations, including anti-token insertion and retiming, can be unified as a mixed integer linear programming problem (MILP) [7], and solved using linear programming tools. Therefore, automatic exploration of pipelines can be achieved by trying different combinations of bypasses added to each of the memory elements of the design, and then automatically pipelining each exploration point [20].…”

Section: B Microarchitectural Explorationmentioning

confidence: 99%

See 1 more Smart Citation

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Cortadella

Galceran-Oms²,

Kishinevsky

et al. 2015

Proc. IEEE

Self Cite

View full text Add to dashboard Cite

Abstract-Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. The paper reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.

show abstract

Section: Re-designing For Average Performancementioning

confidence: 94%

Section: B Microarchitectural Explorationmentioning

confidence: 99%

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Cortadella

Galceran-Oms²,

Kishinevsky

et al. 2015

Proc. IEEE

Self Cite

View full text Add to dashboard Cite

show abstract

“…Retiming and recycling can be successfully applied for systems with early evaluation to achieve better performance [6]. The example from Fig.…”

Section: Early Evaluationmentioning

confidence: 99%

Elastic systems

Cortadella

Galceran-Oms

Kishinevsky

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

Self Cite

View full text Add to dashboard Cite

Elastic systems provide tolerance to the variations in computation and communication delays. The incorporation of elasticity opens new opportunities for optimization using new correct-by-construction transformations that cannot be applied to rigid non-elastic systems.The basics of synchronous and asynchronous elastic systems will be reviewed. A set of behavior-preserving transformations will be presented: retiming, recycling, early evaluation, variablelatency units and speculative execution. The application of these transformations for performance and power optimization will be discussed. Finally, a novel framework for microarchitectural exploration will be introduced, showing that the optimal pipelining of a circuit can be automatically obtained by using the previous transformations.

show abstract

“…The retiming and recycling method [9] captures all transformations from Figure 2(a) in a formal model. A retiming and recycling configuration, RC, assigns an initial number of tokens (possibly negative) and a number of EBs to each edge.…”

Section: Introductionmentioning

confidence: 99%

“…A retiming and recycling configuration, RC, assigns an initial number of tokens (possibly negative) and a number of EBs to each edge. Since analysis of throughput in elastic systems with early evaluation only provides an upper bound, the heuristic method based on mixed integer linear programming presented in [9] finds a set of Pareto-point RCs/ with different trade-offs between cycle time and analytical throughput.…”

Section: Introductionmentioning

confidence: 99%

Automatic microarchitectural pipelining

Galceran-Oms¹,

Cortadella²,

Bufistov³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

Self Cite

View full text Add to dashboard Cite

This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous elastic form, early evaluation, inserting empty buffers, anti-tokens, and retiming. The design exploration is done by solving an optimization problem followed by simulation of solutions. The method is explained on a DLX microprocessor example. The impact of different microarchitectural parameters on the performance is analyzed.

show abstract

Retiming and recycling for elastic systems with early evaluation

Cited by 8 publications

References 15 publications

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Elastic systems

Automatic microarchitectural pipelining

Contact Info

Product

Resources

About