Retiming with interconnect and gate delay

Abstract

In this paper, we study the problem of retiming of

Design and Verification Languages

“…The authors of the latency insensitive design methodologies of [CMSV01,CM04a] use a small MPEG circuit for their experimentations. In contrast, the wire retiming approaches proposed in [LZ03,CYTD03], the architectural retiming technique of [TTBN00] that were described in Section 2.1, a more recent work on concurrent systems [JCK06] In addition, we also present another potential application of the proposed solution technique at the circuit-or logic-level for frequency constrained circuits. Specifically, for designs that have a strict frequency constraint, one solution is to pipeline the circuit, i.e., increase the latencies of the paths that violate the clock period constraint.…”

“…The works of [LZ03,CYTD03] extend retiming by including the interconnect delays, in addition to the gate delays, for pipelining the wires of a circuit. Another work [TTBN00] combines retiming at floorplanning level with module selection to consider wire latencies.…”

Performance-driven register insertion in placement

“…Since retiming was firstly formulated a decade ago, much effort has been made to improve the efficiency of the technique [15] or to apply this technique in various areas like physical planning [4], circuit partitioning [12], power reduction [14], testability [6] and so on. Recently, there are some research efforts on addressing the retiming problem with dominant global wire delays [17,1]. In contrast to the traditional settings of retiming where wire delay is ignored, these new methods can handle both gate and wire delay simultaneously.…”

“…Though the problem of retiming with gate and wire delay has been studied recently [17,1], the placement of registers after retiming is a new challenge. In this paper, we study the problem of realizing a retiming solution on a global netlist by inserting registers in the placement to achieve the target clock period.…”

“…After obtaining the topology tree of a net, we need to find an appropriate position for each register given the constraints in placement (some occupied areas do not allow register insertion) and this problem is known as register placement. Given a placement (we used standard cell design in our experiments) and a retiming solution (we used the technique in [1] to generate the retiming solutions in our experiments), our proposed algorithm can insert registers into the placement solution to preserve the clock period as much as possible. Notice that our algorithm has no dependency of the retiming algorithm being used, as long as it considers wire delay of global nets and gives a retiming solution with a target clock period, retiming labels and the maximum arrival time at each gate output.…”