Reuse distance based performance modeling and workload mapping

Abstract

Modern multicore architectures have multiple cores connected to a hierarchical cache structure resulting in heterogeneity in cache sharing across different subsets of cores. In these systems, overall throughput and efficiency depends heavily on a careful mapping of applications to available cores. In this paper, we study the problem of application-to-core mapping with the goal of trying to improve the overall cache performance in the presence of a hierarchical multi-level cache structure. We propose to sample the memory access patterns of individual applications and build their reuse distance distributions. Further, we propose to use these reuse distance distributions to compute an application-tocore mapping that tries to improve the overall cache performance, and consequently, the overall throughput. We show that our proposed mapping scheme is very effective in practice yielding throughput benefits of about 39% over the worst case mapping and about 30% over the default operating system based mapping. We believe, as larger chip multiprocessors with deeper cache hierarchies are projected to be the norm in the future, efficient mapping of applications to cores will become a vital requirement to extract the maximum possible performance from these systems.

DagTM: An Energy-Efficient Threads Grouping Mapping for Many-Core Systems Based on Data Affinity

“…Moreover, it needs to modify the Linux kernel to implement the proposed framework, which restricts its generality. Muralidhara et al [9] proposed a cache hierarchy-aware application grouping algorithm to find an application-to-core mapping. The work mainly analyzes the memory access relationship between different applications according to the sampling reuse distance distribution on the simulator, and groups the workload on the coarse-grained program level, which could not fully reflect the data interaction characteristics between different threads in the same application.…”

“…Referring to the mapping algorithm in the [9,10], the data affinity sub-trees and memory hierarchy graph are used as input, we realize the thread mapping by static binding of threads to processing cores. The mapping rules are as follows:…”

“…Energies 2016, 9,754 Author Contributions: Tao Ju and Xiaoshe Dong conceived and designed the experiments; Tao Ju and Heng Chen performed the experiments; Tao Ju and Xingjun Zhang analyzed the data; Tao Ju wrote the paper.…”