Reverse engineering camouflaged sequential circuits without scan access

Abstract

Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip from reverse engineering. However, recent work has shown that even camouflaged ICs can be reverse engineered from the observed input/output behaviour of a chip using SAT solvers. However, these so-called SAT attacks have so far targeted only camouflaged combinational circuits. For camouflaged sequential circuits, the SAT attack requires that the internal state of the circuit is controllable and observable via the scan chain. It has been implicitly assumed that restricting scan chain access increases the security of camouflaged ICs from reverse engineering attacks. In this paper, we develop a new attack methodology to decamouflage sequential circuits without scan access. Our attack uses a model checker (a more powerful reasoning tool than a SAT solver) to find a discriminating set of input sequences, i.e., one that is sufficient to determine the functionality of camouflaged gates. We propose several refinements, including the use of a bounded model checker, and sufficient conditions for determining when a set of input sequences is discriminating to improve the run-time and scalabilty of our attack. Our attack is able to decamouflage a large sequential benchmark circuit that implements a subset of the VIPER processor.

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation

“…Bias PUF based scan [38] ScanSAT-resilient large circuits such as s38584 and b19 (even with a key-size of 128). For s38584, the only benchmark common to our and their work, the NSAA tool reportedly crashed [24]. As acknowledged in [24], NSAA is effective only if the ratio of the primary IOs to the SFFs is reasonably large.…”

“…3 Most of the logic locking attacks, including the powerful SAT attack, assume full scan access to a working oracle. We note that there are a few exceptions, such as [24], that launch the attack without scan access; however, as explained further later, the effectiveness of such techniques is quite limited 2. A chip need not be functional to be tested for structural defects.…”

“…An orthogonal line of research is an attack that assumes no scan access [24], herein referred to as NSAA (no scan access attack). NSAA exercises only the primary inputs (and not the SFFs) and observes only the primary outputs (and not the SFFs) of the working chip.…”

“…NSAA exercises only the primary inputs (and not the SFFs) and observes only the primary outputs (and not the SFFs) of the working chip. In [24], NSAA is reported to be successful for 80% of the time for a key-size of 32 bits. Often, the attack can correctly retrieve only a subset of keybits.…”

Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access

“…Comparison with prior attacks. Previously, there has been an attack launched on camouflaged sequential circuits with restricted scan access [32]. To circumvent the blocked scan access, El Massad et al rely on model checker tools to find discriminating input sequences that can be applied through multiple capture cycles to observe the primary output.…”