Reversed-Trellis Tail-Biting Convolutional Code (RT-TBCC) Decoder Architecture Design for LTE

Abstract

Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixed-tail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximum-likelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.

Advanced hybrid algorithms for precise multipath channel estimation in next-generation wireless networks

“…Adiono et al [13] proposed a VLSI architecture for the reversed-trellis TBCC (RT-TBCC) method, highlighting further advancements in this field. This innovative approach revises the traditional directterminating maximum-likelihood decoding procedure to enhance the correction rate.…”

Improving the data recovery for short length LT codes

“…This extra needed packet for LT codes has been approximated to be , while it could be enlarged for small message sizes to reach , [12]. Sevral attempts have been presented in the field of improving the communication systems using channel coding [13][14][15][16][17][18]. In addition, motivating from the decoding treatment which has done by the pattern recognition (PR) [19][20][21][22][23][24][25] to resume decoding when the decoder halt, and the work introduced by [10] for the NUDS, we propose a deterministic encoding (DDG) approach for LT like codes.…”

Improving the Performance of Viterbi Decoder using Window System

“…In [7], Trio and al had proposed a VLSI architecture to implement reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximum-likelihood (ML) decoding process to achieve better correction rate which reduces the computational time and resources compared to the existing solution.…”