2018
DOI: 10.1016/j.microrel.2017.12.039
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Review of bias-temperature instabilities at the III-N/dielectric interface

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Cited by 36 publications
(11 citation statements)
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“…In order to investigate a broad distribution of overall traps through the gate region, which are widely believed to be applicable to GaN HFETs, capture emission time (CET) maps [21,22,23] were extracted using a stress–recovery sequence before and after proton irradiation. A CET map can be constructed from the shift of the I–V or Capacitance -voltage (C–V) characteristics.…”
Section: Resultsmentioning
confidence: 99%
“…In order to investigate a broad distribution of overall traps through the gate region, which are widely believed to be applicable to GaN HFETs, capture emission time (CET) maps [21,22,23] were extracted using a stress–recovery sequence before and after proton irradiation. A CET map can be constructed from the shift of the I–V or Capacitance -voltage (C–V) characteristics.…”
Section: Resultsmentioning
confidence: 99%
“…While there is strong evidence of electron trapping in the gate dielectric as a primary source of V T instability, trapping at interface states located at the dielectric/semiconductor interface is also a possibility. Distinguishing between the two mechanisms is not straightforward [68], and more detailed studies are needed.…”
Section: B Bias-temperature Instability Associated With the Gate Dielectric Of Gan Mis-hemtsmentioning
confidence: 99%
“…It is understood that hysteresis is associated with charging of interface trap states, therefore it offers a measure to quantify the density of these interface trap states. Depending on the AC signal frequency and the up/down voltage sweeping rate, density of a part of slow interface trap states could be estimated [22]. Electrical de-trapping is first performed by maintaining the gate voltage (VG) at -4 V for 2 min, followed by applying a slow ramping DC bias at a speed of 0.…”
Section: Interface Trap State Characterizationmentioning
confidence: 99%
“…During the measurements, the MIS HEMT capacitor is biased above VT,MIS in order to have unchaged 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A c c e p t e d M a n u s c r i p t 9 occupancy of the AlGaN/GaN interface trap states in the bandgap [23]. The Equivalent parallel conductance can be extracted using the measured parallel capacitance (Cp,meas), parallel conductance (Gp,meas), Cox, and ω via the equation derived from MIS capacitor equivalent circuit model [5,35] ( ) 22 ox p,meas p 2 22 p,meas ox p,meas…”
Section: Interface Trap State Characterizationmentioning
confidence: 99%