Review of FinFET Devices and Perspective on Circuit Design Challenges

Maurya, Ravindra Kumar; Bhowmick, Brinda

doi:10.1007/s12633-021-01366-z

Cited by 52 publications

(18 citation statements)

References 21 publications

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“…These limitations emphasize the importance of ongoing research to overcome FinFET challenges. [3][4][5] The Gate-all-around nanosheet field-effect transistor (FET) is an innovative electronic device that has recently gained significant attention. Gate-all-around nanosheet FET is an advanced transistor design that provides exceptional electrostatic control and performance.…”

Section: Introductionmentioning

confidence: 99%

“…FinFET technology, despite its advancements, has drawbacks including complex and costly manufacturing, higher leakage currents, increased power consumption, performance variations due to fin width variability, and reliability issues. These limitations emphasize the importance of ongoing research to overcome FinFET challenges 3–5 . The Gate‐all‐around nanosheet field‐effect transistor (FET) is an innovative electronic device that has recently gained significant attention.…”

Section: Introductionmentioning

confidence: 99%

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Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Sharma

Nath

Deswal³

et al. 2023

Int J Numerical Modelling

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This study's objectives are to deliver a relative analysis of non‐uniformly doped (NUD) and uniformly doped Dual Metal High‐K Schottky nanowire FET (DM‐HK‐SNWFET). Surface potential, subthreshold current, subthreshold swing, and drain current have been expressed and analyzed by resolving 2D Poisson's equation with suitable boundary conditions. The analog performance of the device is verified by examining cut‐off frequency (fT), trans‐conductance frequency product (TFP), gain frequency product (GFP), and gain trans‐conductance frequency product (GTFP). The results show suitable RF circuit parameters with a high switching ratio (≈3 × 109) and low subthreshold swing (61 mV/decade) for NUD‐DM‐HK‐SNWFET. Additionally, linearity frequency of merits (FOMs) and distortion performance are also studied by numerically calculating higher order voltage and current intercept point (VIP2, VIP3, IIP3, IMD3); 1‐dB compression point and Harmonics distortions (HD2 and HD3) using transconductance (gm1) along with its higher derivatives gm2 and gm3. These parameters exhibit high‐level linearity and low‐level distortion at zero crossover points in NUD‐DM‐HK‐SNWFET, making it a better contender for low‐power and high‐performance applications.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Sharma

Nath

Deswal³

et al. 2023

Int J Numerical Modelling

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“…To some applications of the PID controller to control the rehabilitation robots, interested readers may refer to literature [11][12][13][14][15][16], to name a few. Other applications of fuzzy logic and optimization algorithms can be found in literature [17][18][19][20][21]. Dorigo et al [22], using the behavior of ants to find food, have introduced the ant algorithm.…”

Section: Introductionmentioning

confidence: 99%

Development and Control of an upper Limb Rehabilitation Robot via Ant Colony Optimization -PID and Fuzzy-PID Controllers

Mirrashid

Alibeiki

Rakhtala

2022

IJE

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“…Additionally, FinFETs excel in terms of reduced leakage currents and improved subthreshold swing (SS) characteristics, leading to enhanced power efficiency and lower power consumption. 14 This advantage is especially significant in energy-constrained applications, such as mobile devices and batteryoperated systems, IoT applications where FinFETs can enable extended battery life and improved overall performance. 15 The advantages positions FinFETs as a highly promising technology for the future of semiconductor devices.…”

mentioning

confidence: 99%

Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices

Valasa,

Ramakrishna,

Bhukya

et al. 2023

ECS J. Solid State Sci. Technol.

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We outline a original study that represents the first investigation of its kind, focusing on DC and analog/RF performance of structural flavors of FinFET. A total of six structural variations (D1 to D6 devices) in FinFET as per the IRDS 7 nm technology node specifications is explored. Through extensive simulations, our findings demonstrate that the incorporation of gate stack, spacer, and source/drain extension concepts in FinFETs leads to superior performance. The DC performance analysis produced near-ideal SS (~65mV/dec) performance, lower leakage currents, improved switching performance, and reduced DIBL values for D3 to D6 devices owing to the incorporation of gate stack, spacer integration, and source/drain extension doping. In terms of analog/RF performance, the best suitable device is found to be D4 device having designed with 1017 cm-3 n-type lightly-doped source/drain regions, spacer, and gate stack integrations. A significant improvement such as higher gm, reduced gd, enhanced AV, improved fT, GFP, GTFP, and TFP are obtained for D4 device marking a breakthrough in the FinFET designing. Overall, the findings contribute to the advancement of FinFET at 7 nm technology node, opening up new opportunities for applications in various electronic systems demanding improved device performance.

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Review of FinFET Devices and Perspective on Circuit Design Challenges

Cited by 52 publications

References 21 publications

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Analytical analysis and linearity performance of dual metalhigh‐KSchottky nanowireFET(DM‐HK‐SNWFET)

Development and Control of an upper Limb Rehabilitation Robot via Ant Colony Optimization -PID and Fuzzy-PID Controllers

Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices

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