Review of Magnetic Tunnel Junctions for Stochastic Computing

Zink, Brandon R.; Lv, Yang; Wang, Jian Ping

doi:10.1109/jxcdc.2022.3227062

Cited by 13 publications

(4 citation statements)

References 83 publications

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“…The "fixed" layer, which has the stronger magnetic moment, is used as the reference for the "free" layer, whose magnetic moment is more susceptible to being switched. Important MTJ parameters are tunnel magnetoresistance (TMR), which describes the difference in resistance between the parallel (P) and antiparallel (AP) arrangement of the two magnetic layers, and the energy barrier of the free layer, E B, which needs to be overcome to toggle between the two resistance states [27][28][29] .…”

Section: Implementing Probabilistic Bits (P-bits) With Stochastic Mtjsmentioning

confidence: 99%

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

Daniel,

Sun,

Zhang

et al. 2024

Nat Commun

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Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide–semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS2 field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint.

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Section: Implementing Probabilistic Bits (P-bits) With Stochastic Mtjsmentioning

confidence: 99%

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

Daniel,

Sun,

Zhang

et al. 2024

Nat Commun

View full text Add to dashboard Cite

show abstract

“…Different flavors of magnetic p-bits exist [63][64][65][66], for a recent review, see Ref. [67]. Unlike synchronous or trial-based stochasticity (e.g., [68]) that re-…”

Section: Hardware: Physical Implementation Of P-bits a P-bitmentioning

confidence: 99%

A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms

Chowdhury

Grimaldi

Aadit

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The transistor celebrated its 75 th birthday in 2022. The continued scaling of the transistor defined by Moore's Law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms.

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“…[5][6][7] Magnetic random access memories (MRAMs) based on the magnetic tunnel junction (MTJ), the flagship spintronic device, are very promising in this direction. [8][9][10] The MTJ device consists of a thin insulating spacer (non-magnetic) sandwiched between two ferromagnetic (FM) layers, 8 a pinned layer (PL), and a free layer (FL). The spin direction of the PL is immutable due to its high coercivity and cannot be changed by applying the practical magnetic field, while the spin orientation of the FL can be modulated relatively easily.…”

Section: Introductionmentioning

confidence: 99%

Voltage-controlled magnetic anisotropy-based spintronic devices for magnetic memory applications: Challenges and perspectives

Mishra,

Sravani,

Bose

et al. 2024

Journal of Applied Physics

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Electronic spins provide an additional degree of freedom that can be used in modern spin-based electronic devices. Some benefits of spintronic devices include nonvolatility, energy efficiency, high endurance, and CMOS compatibility, which can be leveraged for data processing and storage applications in today's digital era. To implement such functionalities, controlling and manipulating electron spins is of prime interest. One of the efficient ways of achieving this in spintronics is to use the electric field to control electron spin or magnetism through the voltage-controlled magnetic anisotropy (VCMA) effect. VCMA avoids the movement of charges and significantly reduces the Ohmic loss. This article reviews VCMA-based spintronic devices for magnetic memory applications. First, we briefly discuss the VCMA effect and various mechanisms explaining its physical origin. We then mention various challenges in VCMA that impede it for practical VCMA-based magnetic memory. We review various techniques to address them, such as field-free switching operation, write error rate improvement, widening the operation window, enhancing the VCMA coefficient, and ensuring fast-read operation with low read disturbance. Finally, we draw conclusions outlining the future perspectives.

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Review of Magnetic Tunnel Junctions for Stochastic Computing

Cited by 13 publications

References 83 publications

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms

Voltage-controlled magnetic anisotropy-based spintronic devices for magnetic memory applications: Challenges and perspectives

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