Review of progress in extreme ultraviolet lithography masks

Abstract

Extreme ultraviolet lithography (EUVL) is a leading next generation lithography technology. Significant progress has been made in developing mask fabrication processes for EUVL. The mask blank for EUVL consists of a low thermal expansion material substrate having a square photomask form factor that is coated with Mo/Si multilayers. SEMI standards are being developed for mask substrates and mounting. Several commercial suppliers are developing polishing processes for LTEM substrates, and they are progressing toward meeting the requirements for flatness, surface roughness, and defects defined in the a draft SEMI standard. One of the challenges in implementing EUVL is to economically fabricate multilayer-coated mask blanks with no printable defects. Significant progress has been made in developing mask blank multilayer coating processes with low added defect density. Besides lowering the added defect density, methods to reduce defect printability, such as defect compensation and buffer layer smoothing, are being developed. Experiments indicate that Mo/Si multilayers that are deposited with ion beam deposition tend to smooth substrate defects, and buffer layer films are being designed to enhance this effect. Targets for buffer layer smoothing are being defined using defect printability simulations. A method for using an electron beam to repair substrate defects after multilayer coating is also being investigated. The mask patterning process for EUVL is nearly the same as that for conventional binary optical lithography masks. EUVL mask patterning efforts are focused on developing the EUV-specific aspects of the patterning process. Eight absorbers have been evaluated against the requirements for EUVL masks, and two absorbers appear most promising. Conventional membrane pellicles are not practical for EUVL, so thermophoretic protection is being developed. Experiments have indicated that thermophoretic protection is effective for >125 nm particles down to at least 50 mTorr pressure. A removable pellicle will be used to protect the mask from defects at all times except during wafer exposure.

Evaluation of protection schemes for extreme ultraviolet lithography (EUVL) masks against top–down aerosol flow

“…The challenge, however, is that conventional pellicles cannot be used in the EUVL technology because of high absorption of EUV radiation in the pellicles. As a substitute, it was proposed to use a removable pellicle during all stages of mask handling, shipping and storage except for the scanning exposure in a process chamber (Diefendorff, 2000;Hector & Mangat, 2001;Litt, Hector, & Seidel, 2003). When the pellicle is removed for scanning exposure at low pressure, the EUVL masks may be protected using electrostatic fields (Moors & Heerens, 2002), thermophoresis Dedrick, Beyer, Rader, Klebanoff, & Leung, 2005;, or reverse flow to decelerate the particles coming towards the critical surface (Kim, Fissan, Asbach, Yook, Wang et al, 2006).…”

A new pre-alignment approach based on Four-Quadrant-Photo-Detector for IC mask

“…Similarly, for U b−t in (2), if the mark's center deviates to the bottom, U b−t > 0, and U b−t < 0 otherwise. If the alignment mark's pose is symmetric about both the Xand Y -axes of FQPD, as shown in Fig.…”

“…Photolithography takes a leading role in integrated circuit mass production. Report [2] shows that more than 20 lithography procedures are required to fabricate a complicated chip, where the alignment of different layers with respect to each other with nanometer precision is very important. In the arts of photolithography, the pre-alignment of IC mask's pose plays an important role in the course of mask loading, as it directly affects the accuracy of lithography [3−8] .…”

Mask availability for next-generation lithography

“…A simple Cr abTr2nsmlcsinn SEM sorber on Si02 buffer has become an early choice for imaging studies because of its compatibility with existing photomask processes. [15] The MCoC has fabricated several ETJVL masks with this choice of materials including masks for the EUV-LLC's Engineering Test Stand and a gate level from a high-density SRAM device layer at 45 nm lithography node dimensions.…”