Extreme ultraviolet lithography (EUVL) is a leading next generation lithography technology. Significant progress has been made in developing mask fabrication processes for EUVL. The mask blank for EUVL consists of a low thermal expansion material substrate having a square photomask form factor that is coated with Mo/Si multilayers. SEMI standards are being developed for mask substrates and mounting. Several commercial suppliers are developing polishing processes for LTEM substrates, and they are progressing toward meeting the requirements for flatness, surface roughness, and defects defined in the a draft SEMI standard. One of the challenges in implementing EUVL is to economically fabricate multilayer-coated mask blanks with no printable defects. Significant progress has been made in developing mask blank multilayer coating processes with low added defect density. Besides lowering the added defect density, methods to reduce defect printability, such as defect compensation and buffer layer smoothing, are being developed. Experiments indicate that Mo/Si multilayers that are deposited with ion beam deposition tend to smooth substrate defects, and buffer layer films are being designed to enhance this effect. Targets for buffer layer smoothing are being defined using defect printability simulations. A method for using an electron beam to repair substrate defects after multilayer coating is also being investigated. The mask patterning process for EUVL is nearly the same as that for conventional binary optical lithography masks. EUVL mask patterning efforts are focused on developing the EUV-specific aspects of the patterning process. Eight absorbers have been evaluated against the requirements for EUVL masks, and two absorbers appear most promising. Conventional membrane pellicles are not practical for EUVL, so thermophoretic protection is being developed. Experiments have indicated that thermophoretic protection is effective for >125 nm particles down to at least 50 mTorr pressure. A removable pellicle will be used to protect the mask from defects at all times except during wafer exposure.

The Engineering Test Stand (ETS) is a developmental lithography tool designed to demonstrate full-field EUV imaging and provide data for commercial-tool development. In the first phase of integration, currently in progress, the ETS is configured using a developmental projection system, while fabrication of an improved projection system proceeds in parallel. The optics in the second projection system have been fabricated to tighter specifications for improved resolution and reduced flare. The projection system is a 4-mirror, 4x-reduction, ring-field design having a numeral aperture of 0.1, which supports 70 nm resolution at a k 1 of 0.52. The illuminator produces 13.4 nm radiation from a laser-produced plasma, directs the radiation onto an arc-shaped field of view, and provides an effective fill factor at the pupil plane of 0.7. The ETS is designed for fullfield images in step-and-scan mode using vacuum-compatible, magnetically levitated, scanning stages. This paper describes system performance observed during the first phase of integration, including static resist images of 100 nm isolated and dense features.

In two separate experiments, we have successfully demonstrated the transfer of dense- and loose-pitch line/space (L/S) photoresist features, patterned with extreme ultraviolet (EUV) lithography, into an underlying hard mask material. In both experiments, a deep-UV photoresist (∼90 nm thick) was spin cast in bilayer format onto a hard mask (50–90 nm thick) and was subsequently exposed to EUV radiation using a 10× reduction EUV exposure system. The EUV reticle was fabricated at Motorola (Tempe, AZ) using a subtractive process with Ta-based absorbers on Mo/Si multilayer mask blanks. In the first set of experiments, following the EUV exposures, the L/S patterns were transferred first into a SiO2 hard mask (60 nm thick) using a reactive ion etch (RIE), and then into polysilicon (350 nm thick) using a triode-coupled plasma RIE etcher at the University of California, Berkeley, microfabrication facilities. The latter etch process, which produced steep (>85°) sidewalls, employed a HBr/Cl chemistry with a large (>10:1) etch selectivity of polysilicon to silicon dioxide. In the second set of experiments, hard mask films of SiON (50 nm thick) and SiO2 (87 nm thick) were used. A RIE was performed at Motorola using a halogen gas chemistry that resulted in a hard mask-to-photoresist etch selectivity >3:1 and sidewall profile angles ⩾85°. Line edge roughness (LER) and linewidth critical dimension (CD) measurements were performed using Sandia’s GORA© CD digital image analysis software. Low LER values (6–9 nm, 3σ, one side) and good CD linearity (better than 10%) were demonstrated for the final pattern-transferred dense polysilicon L/S features from 80 to 175 nm. In addition, pattern transfer (into polysilicon) of loose-pitch (1:2) L/S features with CDs⩾60 nm was demonstrated.

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