Review on VLSI design using optimization and self-adaptive particle swarm optimization

Kumar, Sandeep; Rao, P. V.; Sharath, H.A.; M, Sachin B; Ravi, U.S.; Monica, B.V.

doi:10.1016/j.jksuci.2018.01.001

Cited by 23 publications

(13 citation statements)

References 112 publications

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“…Very Large Scale Integration (VLSI) is a process of forming an Integrated Circuit (IC) by incorporating thousands of transistors into a single chip [1]. As integration continues to increase, more and more features, even a complete system can be integrated into a single chip.…”

Section: Dementioning

confidence: 99%

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A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

et al. 2020

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Routing is a complex and critical stage in the physical design of Very Large Scale Integration (VLSI), minimizing interconnect length and delay to optimize overall chip performance. With the rapid development of modern technology, VLSI routing faces enormous challenges such as large delay, high congestion, and high-power consumption. As a rising optimization method, Swarm Intelligence (SI) inspired from collective intelligence behaviors through cooperation or interaction with the environment provides effectiveness and robustness for solving NP-hard problems. Many researchers have consequently used SI techniques to solve routing-related problems in VLSI. This paper reviews the application of several SI techniques to the VLSI routing filed. Firstly, five commonly used SI techniques and related models, and three classic routing problems are described: Steiner tree construction, global routing and detailed routing. Then an overview of the current state of this field is given according to the above categories, and the survey offers informative discussions from five aspects: 1) Steiner minimum tree construction; 2) wirelength-driven routing; 3) obstacle-avoiding routing; 4) timing-driven routing; 5) power-driven routing. Finally, under three new technology models: X-architecture, multiple dynamic supply voltage and via-pillar, the future development trends are pointed as follows: 1) suggesting suitable SI techniques to specific routing problems for advanced technology models; 2) exploring new and available SI techniques that have not yet been applied to VLSI routing.

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Section: Dementioning

confidence: 99%

“…} is mutant vector. The indices r 1 , r 2 , r 3 , r 4 , r 5 are mutually exclusive integers randomly generated within the range [1,NP], and these indices are randomly generated once for each mutant vector. The scaling factor F is a positive control parameter for scaling the difference vector.…”

Section: A: Mutation Operationmentioning

confidence: 99%

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

et al. 2020

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“…The design and theoretical concept of power dissipation limits and switching selectivity has strong face validity in recent publications such as; the study the VLSI design using optimization and self-adaptive particle swarm optimization for recent trends in the advancements and further developments of VLSI design is presented in (Kumar et al, 2018), a specific method for finding optimal combination of the supply and body bias voltages to the processor core and memory is proposed in (Okuhara et al, 2015), design an application circuit integrated with a proposed built-in body bias generation (BBG) circuits in a 65-nm process is presented in (Kamae et al, 2015), determination and analysis of the best switching management strategy for dynamic set of operating environment in terms of process choices, circuit activity, and temperatures is presented in (Puschini et al, 2016), the trade-offs in energy and performance when running a wide range of applications are explores in (Pahlevan et al, 2016), a method and flow for implementing a clock tree inside an application-specific integrated circuit (ASIC) for near-threshold/subthreshold technology with optimal power dissipation is presented in (Zangi and Feldman, 2017), finally, a new logic family called dual mode transmission gate diffusion input logic (DMTGDI) was introduced in (Pashaki and Shalchian, 2016) that has superior performance and less energy consumption both in subthreshold and above subthreshold regions.…”

Section: Zanco Journal Of Pure and Applied Sciences 2019mentioning

confidence: 99%

The Complete Switching Circuit Design for CPU Joint Body Biasing and Supply Voltage Scaling

2019

ZJPAS

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The modern CPU technology scaling with increasing transistor density causes an exponential growth of both dynamic and static power dissipations that affecting the microprocessor's performance. The body bias voltage (VBB) and supply voltage (VDD) extent to decrease to maintain the low power requirements. Joint body biasing and voltage scaling is an efficient technique that reduces the power dissipation of CPUs and high performance digital devices when peak performance is unneeded. Switching networks have become an essential component in the design of digital ICs that require the ability to control and select a specified threshold voltage/body-bias and supply voltages (VTH/VBB-VDD) for the microprocessor chip. This paper presents a complete design of a switching network for joint body biasing and supply voltage scaling (VBB-VDD), which is consistent in allowing compact low power consumption and low temperatures in the core of high-performance processors. The results show the roles and effectiveness of the switching network that adaptively selects the VTH/VBB-VDD sets for different workloads and simulation environments and all temperature ranges.

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“…Optimization algorithms in integrated circuit design may be split into three main categories: Bio-inspired optimizations which encompass evolutionary algorithms and swarm intelligence algorithms, deterministic algorithms, and other optimization techniques that do not fit in the previous two categories such as simulated annealing, convex optimization, and greedy algorithms [5].…”

Section: Optimization Algorithmsmentioning

confidence: 99%

Particle Swarm Optimization of a Rail-to-Rail Delay Element for Maximum Linearity

Gauci

Gatt

Casha

et al. 2019

2019 6th International Conference on Control, Decision and Information Technologies (CoDIT)

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This paper illustrates the use of the Particle Swarm Optimization (PSO) algorithm to maximize the linearity of a rail-to-rail delay element. Previous approaches relied on approximating the piecewise time-delay model of the delay element through either the Newton Polynomial or the Lagrange Polynomial methods. While adequate linearity was achieved in both cases, this could be further improved. This work successfully employed the PSO algorithm to improve the linearity by reducing the mean square error such that the delay element exhibits a spurious-free dynamic range of 29.62 dB, with a delay range of 170.4 ns. The results were verified in Cadence using the X-FAB 0.18 µm technology.

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Review on VLSI design using optimization and self-adaptive particle swarm optimization

Cited by 23 publications

References 112 publications

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

The Complete Switching Circuit Design for CPU Joint Body Biasing and Supply Voltage Scaling

Particle Swarm Optimization of a Rail-to-Rail Delay Element for Maximum Linearity

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