Revisiting hash table design for phase change memory

Debnath, Biplob; Haghdoost, Alireza; Kadav, Asim; Khatib, Mohammed G.; Ungureanu, Cristian

doi:10.1145/2819001.2819002

Cited by 28 publications

(19 citation statements)

References 23 publications

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“…Level hashing is a variant of Bucketized Cuckoo hashing (BCH) [18], [30], [31]. It is designed to reduce write operations in consideration of the PM characteristics.…”

Section: ) Hash-based Index Structuresmentioning

confidence: 99%

“…To recover from system failure, the index structure of an IMDB should be able to reconstruct the consistent state from the remaining data in memory at any point. For this, several PM-aware index structures have been proposed [2]- [18]. However, the PM-aware indexes commonly send writes down to the PM using the explicit cache flush and memory fence instructions to ensure write-ordering whenever the structure is modified.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Optimization of Persistent Memory Index Structures’ Write Amplification

et al. 2021

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Using persistent memory (PM) for an in-memory database (IMDB) system significantly extends data processing capacity and reduces service downtime for the recovery process in case of system failure. However, it requires an index structure tailored for the characteristics of PM to recover the consistent state from system failure. The processor flushes data with the cache line size to the memory controller, whereas the PM media writes with the media-write unit size, which is four times larger than the cache line size. This mismatch in write sizes amplifies the quantity of data written by an index structure at the physical media level. Additionally, the PM-aware index structures explicitly and frequently flush cache lines to ensure memory write orders, which worsen the write amplification factor. The write amplification not only degrades the performance but also shortens the lifespan of PM media. This study analyzes the write amplification and performance of various PM-aware index structures at the memory controller and physical media levels. Furthermore, this paper proposes four optimization techniques based on our observation: removal of unintended bloat, cache flush coalescing, early eviction of volatile data, and XPLine-aware unit sizing. Our analysis demonstrated that up to 3.9 times as many writes could occur depending on the choice of the index structure. We also revealed that the proposed optimization techniques could save up to 51% of physical media write operations and improve throughput by up to 63%.

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“…Level hashing is a variant of Bucketized Cuckoo hashing (BCH) [18], [30], [31]. It is designed to reduce write operations in consideration of the PM characteristics.…”

Section: ) Hash-based Index Structuresmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis and Optimization of Persistent Memory Index Structures’ Write Amplification

et al. 2021

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“…Memristors have also been proposed for building byteaddressable non-volatile memories. There have been various works centered around system support for non-volatile memory, including file systems [30], memory allocators [11,83], programming models [16,27,106], durable data structures [31,55,113], representation of pointers [18,28,34,35], and architecture support [60,80,82,99].…”

Section: Related Workmentioning

confidence: 99%

Puma

Ankit

Hajj

Chalamalasetti

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

287

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Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set of neural network applications.We present the Programmable Ultra-efficient Memristorbased Accelerator (PUMA) which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads. PUMA's microarchitecture techniques exposed through a specialized Instruction Set Architecture (ISA) retain the efficiency of in-memory computing and analog circuitry, without compromising programmability.We also present the PUMA compiler which translates high-level code to PUMA ISA. The compiler partitions the computational graph and optimizes instruction scheduling and register allocation to generate code for large and complex workloads to run on thousands of spatial cores.We have developed a detailed architecture simulator that incorporates the functionality, timing, and power models of * Work done while at University of Illinois at Urbana-Champaign PUMA's components to evaluate performance and energy consumption. A PUMA accelerator running at 1 GHz can reach area and power efficiency of 577 GOPS/s/mm 2 and 837 GOPS/s/W, respectively. Our evaluation of diverse ML applications from image recognition, machine translation, and language modelling (5M-800M synapses) shows that PUMA achieves up to 2,446× energy and 66× latency improvement for inference compared to state-of-the-art GPUs. Compared to an application-specific memristor-based accelerator, PUMA incurs small energy overheads at similar inference latency and added programmability.

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“…There has been additional work on indices that reduce writes to byte-addressable NVM, to reduce its wear [11,14,18,32]. Prior research has also explored using using differential logging [10,20,21], to only log modified bytes to avoid excessive writes in NVM.…”

Section: Nvm For Key-value Storesmentioning

confidence: 99%

Reducing DRAM footprint with NVM in Facebook

Eisenman

Gardner

AbdelRahman

et al. 2018

Proceedings of the Thirteenth EuroSys Conference

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Popular SSD-based key-value stores consume a large amount of DRAM in order to provide high-performance database operations. However, DRAM can be expensive for data center providers, especially given recent global supply shortages that have resulted in increasing DRAM costs. In this work, we design a key-value store, MyNVM, which leverages an NVM block device to reduce DRAM usage, and to reduce the total cost of ownership, while providing comparable latency and queries-per-second (QPS) as MyRocks on a server with a much larger amount of DRAM. Replacing DRAM with NVM introduces several challenges. In particular, NVM has limited read bandwidth, and it wears out quickly under a high write bandwidth. We design novel solutions to these challenges, including using small block sizes with a partitioned index, aligning blocks post-compression to reduce read bandwidth, utilizing dictionary compression, implementing an admission control policy for which objects get cached in NVM to control its durability, as well as replacing interrupts with a hybrid polling mechanism. We implemented MyNVM and measured its performance in Facebook's production environment. Our implementation reduces the size of the DRAM cache from 96 GB to 16 GB, and incurs a negligible impact on latency and queries-per-second compared to MyRocks. Finally, to the best of our knowledge, this is the first study on the usage of NVM devices in a commercial data center environment.

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Revisiting hash table design for phase change memory

Cited by 28 publications

References 23 publications

Analysis and Optimization of Persistent Memory Index Structures’ Write Amplification

Analysis and Optimization of Persistent Memory Index Structures’ Write Amplification

Puma

Reducing DRAM footprint with NVM in Facebook

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