Proceedings of the Thirteenth EuroSys Conference 2018
DOI: 10.1145/3190508.3190524
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Reducing DRAM footprint with NVM in Facebook

Abstract: Popular SSD-based key-value stores consume a large amount of DRAM in order to provide high-performance database operations. However, DRAM can be expensive for data center providers, especially given recent global supply shortages that have resulted in increasing DRAM costs. In this work, we design a key-value store, MyNVM, which leverages an NVM block device to reduce DRAM usage, and to reduce the total cost of ownership, while providing comparable latency and queries-per-second (QPS) as MyRocks on a server wi… Show more

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Cited by 99 publications
(64 citation statements)
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“…This polling method is implemented in Linux 4.4 kernel, but from 4.10 kernel, Linux supports a hybrid polling [23,49]. The hybrid polling sleeps for a while in an attempt to reduce the number of polling the queues.…”
Section: ) I/o Completion Methods For Nvmementioning
confidence: 99%
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“…This polling method is implemented in Linux 4.4 kernel, but from 4.10 kernel, Linux supports a hybrid polling [23,49]. The hybrid polling sleeps for a while in an attempt to reduce the number of polling the queues.…”
Section: ) I/o Completion Methods For Nvmementioning
confidence: 99%
“…The study proposed to employ a polling-based synchronous I/O service in high performance systems. Similarly, [14,23,43,49,54,68,76,79] advocate to employ the polledmode system for fast NVMe devices. To use the polling in an efficient manner, [23,49,79] proposed different types of a hybrid polling, which combines the current interruptdriven method with the polling by being aware of application characteristics or runtime environment.…”
Section: How Much Can Spdk Reduce the System-level Latency Under Amentioning
confidence: 99%
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“…Use of heterogeneous memory to reduce DRAM has been studied in the past. Facebook has used SSDs to reduce the DRAM footprint of databases [13]. Bandana [14] uses SSD based persistent memory to store deep learning embedding tables [10] with DRAM as a small software cache.…”
Section: Introductionmentioning
confidence: 99%
“…Second, persistent data structures [1,4,9,14,18] enable direct fine-grained writes to NVM by issuing out-of-place writes and relying on instruction ordering (SFENCE) and eagerly flushing cache lines (CLFLUSH/CLWB) to make the operation visible (usually by flipping a validity bit). Third, buffer managers were proposed to integrate NVM with the storage hierarchy below DRAM and above SSD [5,15,16]. These approaches access data on DRAM, and therefore they have full control of when data is persisted.…”
Section: Introductionmentioning
confidence: 99%