Revisiting level-0 caches in embedded processors

Abstract

Level-0 (L0) caches have been proposed in the past as an inexpensive way to improve performance and reduce energy consumption in resource-constrained embedded processors. This paper proposes new L0 data cache organizations using the assumption that an L0 hit/miss determination can be completed prior to the L1 access. This is a realistic assumption for very small L0 caches that can nevertheless deliver significant miss rate and/or energy reduction. The key issue for such caches is how and when to move data between the L0 and L1 caches. The first new cache, a flow cache, targets a conflict miss reduction in a direct-mapped L1 cache. It offers a simpler hardware design and uses on average 10% less dynamic energy than the victim cache with nearly identical performance. The second new cache, a hit cache, reduces the dynamic energy consumption in a set-associative L1 cache by 30% without impacting performance. A variant of this policy reduces the dynamic energy consumption by up to 50%, with 5% performance degradation.

A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache

“…2. The main architecture for our WF cache is similar to the ones previously proposed [10,11]. These techniques are mainly for performance improvement and energy reduction by exploiting the fast hit latency and low access energy of the filter cache.…”

“…In this paper, we propose two different line allocation policies for the WF cache: WF_RD and WF_WR. The WF_RD policy is similar to the allocation policy of Hit Cache [10]. The WF_RD policy does not allocate the cache line to the WF cache along with the block (line) fill in the L1 data cache (i.e., when there is a cache miss).…”

“…Moreover, thanks to fast hit latency of WF cache, it brings a little performance benefit. The main architecture of our WF cache is similar to the conventional filter caches [10,11]. However, we use novel WF cache allocation and access policies optimized for STTRAM-based L1 data caches.…”

Improving data cache performance using Persistence Selective Caching

“…A majority of references are thus serviced by the larger L1D cache, and consequently, the relatively shorter latency and energy per access of the assist cache remain unexploited. Duong's L0 scheme (I1P101 in particular) [2] and the HitME cache [5] are examples of cache organizations that service a majority of data references through an assist placed alongside the L1D. In these proposals, any cache line that is referenced atleast once in the L1D is immediately moved to the assist.…”

Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor

“…In this structure, a predictor is added to the filter cache system and the predictor selects the access path between L1 cache and filter cache. In addition, new policies about cache placement have been introduced to increase hit rate of L1 cache or filter cache [5], [6]. According to the policies, a cache line is inserted into either L1 cache or filter cache on a cache miss.…”