Revisiting the doping requirement for low power junctionless MOSFETs

Abstract

In this work, we revisit the requirement of higher channel doping ( 10 19 cm −3 ) in junctionless (JL) double gate MOSFETs. It is demonstrated that moderately doped (10 18 cm −3 ) ultra low power (ULP) JL transistors perform significantly better than heavily doped (10 19 cm −3 ) devices. JL MOSFETs with moderate doping results in the spreading out of carriers across the entire silicon film instead of being localized at the center of the film. This improves gate controllability leading to higher on-off current ratio and lower intrinsic delay for ULP subthreshold logic applications. Additional benefits of using a channel doping concentration of 10 18 cm −3 instead of conventional heavily doped design is the significant reduction in threshold voltage sensitivity values (by ∼70-90%) with respect to film thickness and gate oxide thickness. Further improvement in ULP performance metrics can be achieved by limiting the source/drain implantation away from the gate edge. This design, specifically for ULP, allows the requirement of gate workfunction to be reduced from p + -poly (∼ 5.1 eV) to near about midgap values (∼ 4.8 eV). On-off current ratio and intrinsic delay for optimized JL devices are compared for low standby power projections of the technological roadmap. A 6T-SRAM cell operating at 0.8 V with 25 nm JL devices exhibits a static noise margin of 151 mV with gate workfunction offset of 0.2 eV with respect to midgap value (4.72 eV). The results highlight new viewpoints for realizing improved low power JL transistors.

Improved performance of nanoscale junctionless transistor based on gate engineering approach

“…It can be seen that V TH is highly sensitive to all the listed parameters. Moreover, sensitivity of V TH towards film thickness T SI is highest while it is minimum for gate length variation [36]. However, a change in N D only slightly affects SS, DIBL and I ON /I OFF .…”

Junctionless Transistors: State-of-the-Art

“…A simpler approach is doping concentration engineering. It was reported that a concentration of 1 × 10 18 cm −3 can significantly reduce the threshold voltage sensitivity by 70-90% with respect to the device layer and gate oxide thickness [68]. Graded doping profile can reduce I o f f by six orders of magnitude [71].…”

Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET

“…The JL-FinFET has many inherent advantages, but the critical constraint during the fabrication is achieving high uniform doping in the device layer. This complexity is increased even more for nonplanar architectures such as FinFET as the fin's doping has to be accomplished in a three-dimensional pattern, resulting in non-uniform doping around the fin region [16]. The generic analytical doping is a Gaussian doping profile from which other doping distributions can be derived by tuning specific parameters of Gaussian distribution as required [17].…”