2010
DOI: 10.1016/j.mee.2009.08.026
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RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

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Cited by 26 publications
(16 citation statements)
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“…The inductance linearly increases from 0.13 to 0.33 nH for 40-to 320--long lines, with an inductance per meter of for the line. This value is fully consistent with standard values for CPWs found in literature for similar dimensions [5], [7], [16]. The extracted inductance of one via is at frequencies below 100 MHz.…”
Section: Inductancesupporting
confidence: 91%
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“…The inductance linearly increases from 0.13 to 0.33 nH for 40-to 320--long lines, with an inductance per meter of for the line. This value is fully consistent with standard values for CPWs found in literature for similar dimensions [5], [7], [16]. The extracted inductance of one via is at frequencies below 100 MHz.…”
Section: Inductancesupporting
confidence: 91%
“…The main contribution to the total inductance depends on the length of the line. This inductance value is proportionally two times lower than inductance obtained for moderate aspect ratio vias described in [6] and [7], and 500-1000 times lower than wire bonding, making TSV very attractive for 3D integration. The resonance peaks fall at the resonance peaks already described in the resistance curves.…”
Section: Inductancementioning
confidence: 66%
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“…Vias are interconnects commonly found on multilayer printed or integrated circuits [13][14]. Often, they provide some path to ground or to other device via some RDL (Re-Distribution Layer).…”
Section: Via Electromagnetic Behaviourmentioning
confidence: 99%