RF electro-thermal modeling of LDMOSFETs for power-amplifier design

Akhtar, S.; Roblin, Patrick; Lee, Sun Young; Ding, Xiaohui; Yu, Shuang; Kasick, J.; Strahler, J.

doi:10.1109/tmtt.2002.1006418

Cited by 7 publications

(2 citation statements)

References 13 publications

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“…To explore the impact of the source impedance in further detail, let us consider the example of a power LDMOSFET [13] with 224 fingers each of gate width 90 m, for a total lateral source resistance of 1.3 . In Fig.…”

Section: Numerical Resultsmentioning

confidence: 99%

Modeling of distributed parasitics in power FETs

Lee

Roblin

Lopez³

2002

IEEE Trans. Electron Devices

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A distributed circuit analysis of power FETs accounting for the lateral source parasitic impedance in addition to the lateral drain and gate parasitic impedances is presented. Both a numerical solution and an exact analytic solution are derived. Using the exact analytic solution, approximate equivalent circuits are derived for FETs of short gate width for two common types of boundary conditions. When the gate and drain terminals are located on opposite sides of the distributed FET, the lateral source parasitic impedance can be represented for short gate width FETs by an equivalent circuit with a negative series impedance in series with the source terminal. The practical consequences on parameter extraction for device modeling are discussed. The availability of an exact analytic solution for the distributed FET should also assist with the synthesis of traveling wave FETs.

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Section: Numerical Resultsmentioning

confidence: 99%

Modeling of distributed parasitics in power FETs

Lee

Roblin

Lopez³

2002

IEEE Trans. Electron Devices

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“…From a practical point of view, the significance of the high-temperature characterization can be seen in the context of the sweet spots appearing in FET-based PAs. [43][44][45][46][47][48][49] As well-known, sweet spots are highly desired to enable improvement in the linearity-efficiency tradeoff. Although the control of the sweet-spot location and level can be pursued via proper selection of the specific operating condition; the sweet-spot behavior can be drastically affected by many parameters, including the temperature.…”

Section: Introductionmentioning

confidence: 99%

Experimental insight into the temperature effects on DC and microwave characteristics for a GaAs pHEMT in multilayer 3‐D MMIC technology

Alim

Rezazadeh

Crupi

2020

Int J RF Microw Comput Aided Eng

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This paper is focused on studying the behavior of a GaAs pseudomorphic high electron mobility transistors (pHEMT) with respect to the temperature. The tested pHEMT is realized using the multilayer three‐dimensional (3‐D) monolithic microwave integrated circuit (MMIC) technology. The analysis is based on temperature‐dependent on‐wafer measurements carried out from 298 K to 373 K. The experiments consist of DC characteristics and scattering parameters in the broad frequency range from 45 MHz to 40 GHz. The effect of the temperature on the measured transistor performance is analyzed in detail and then, to gain a better insight and understanding of the device behavior, the achieved measurements are used for extraction and validation of a small‐signal equivalent‐circuit model for different temperature conditions. This study shows that, by heating the studied device, the observed performance variations depend remarkably on the selected bias condition. In particular, the output current and transconductance are degraded at higher gate‐source voltage and improved as the transistor is driven towards the pinch‐off. This is due to the counterbalancing of temperature‐dependent effects contributing in opposite ways to the resultant behavior of the transistor. Therefore, depending on the given application, an appropriate selection of the bias and temperature conditions is essential to guarantee adequate transistor performance.

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