RF front-end architecture for a triple-band CMOS GPS receiver

Jo, Ikkyun; Bae, Jinho; Matsuoka, Toshimasa; Ebinuma, Takuji

doi:10.1016/j.mejo.2014.10.001

Cited by 8 publications

(7 citation statements)

References 20 publications

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“…To overcome the limitations mentioned above, extensive research on the CMOS (complementary metal-oxide semiconductor) integration of the dual-frequency radio frequency (RF) front-end for GNSS has been performed [13][14][15][16][17][18][19]. So far, most of the designs either offer only configurability between different bands of GNSS without the possibility of simultaneous multi-frequency reception of all constellations by a single chip [13,15,16,19] or they do not receive all bands from the most popular GNSS systems and focus only on L1/E1 and L5/E5a reception [14,17].…”

Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

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A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

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Section: Introductionmentioning

confidence: 99%

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Borejko

Marcinek

Siwiec

et al. 2020

Sensors

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“…The CMOS process is the most commonly used technology for GPS receivers [10] - [25]. However, [26] has used bipolar technology and [8], [9], [30] have used the BiCMOS technology.…”

Section: B Off-chip Componentsmentioning

confidence: 99%

Advanced System Analysis and Survey on the GPS Receiver Front End

Kumari

Bhatt

2022

IEEE Access

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A fully integrated GPS receiver system can enable unique system capabilities by synthesizing both receiver front end and baseband on the same chip, leading to lower area overhead and higher integration. A review on the GPS receiver system that focuses on front end design is presented in the paper. The first section discusses the various global navigation satellite system (GNSS), followed by the GPS working section. Afterwards, the paper discusses the previous works on the GPS receiver front end design. It provides a detailed survey and classification of various receiver architecture, including the LNA, mixer, filter, and ADC topologies. Besides, several image rejection techniques are presented for more than 50 GPS receivers. The various performance parameters of the GPS receiver front end in the literature are presented with the graphical view in the state-of-the-art discussion section. This literature survey provides the most extensive compilation to date of the various topologies, techniques and explains their implementation in the GPS receiver system. A new figure of merit that includes all the system parameters is proposed. The FOM can be an excellent reference to enhance the research work in the field of GPS receivers. In the end, the paper describes the possible research scope and challenges associated with the design of the GPS receiver front end.INDEX TERMS global navigation satellite system (GNSS), image rejection, RF front end, sensitivity, spurious free dynamic range (SFDR), wireless communication.

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“…Traditionally, low-IF architectures were adopted in GNSS RF front-end [1,2,3,4,5,7,8] to relax image-rejection requirements and deal with problems such as dc offset and flicker noise. To further achieve even higher image rejection ratio (IMRR) performance, digital calibration techniques were employed to improve the matching between I and Q branches [4,5,9]. A typical architecture employs a pseudo-differential low noise amplifier (LNA) to perform single-ended-to-differential transformation [1,2,3] and an active mixer to realize down-conversion [1,2,3,4,5].…”

Section: Introductionmentioning

confidence: 99%

A RF CMOS GNSS receiver with a passive mixer for GPS L1/Galileo E1/Compass B1 band

Wang

Gao²,

et al. 2018

IEICE Electron. Express

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This paper presents the design and implementation of a 180 nm CMOS reconfigurable global navigation satellite system receiver, supporting GPS L1, Galileo E1 and Compass B1 bands. The low-IF receiver incorporates a pseudo-differential low-noise amplifier, a double-balanced passive mixer, a pair of trans-impedance amplifiers, a complex band-pass filter, an analog-to-digital converter and an automatic gain control. A phase-locked loop is integrated to provide 25% duty-cycle quadrature clock signals. The RF front-end achieves a maximum gain of 107.2 dB with a dynamic range of 78 dB, a noise figure of 1.8 dB and an image rejection ratio of 39.1 dB.

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RF front-end architecture for a triple-band CMOS GPS receiver

Cited by 8 publications

References 20 publications

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Advanced System Analysis and Survey on the GPS Receiver Front End

A RF CMOS GNSS receiver with a passive mixer for GPS L1/Galileo E1/Compass B1 band

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