"RF-on" polysilicon etch defectivity monitor for manufacturing and process development

Rao, Suraj; Lavangkul, S.; Laaksonen, Timo; Ali, Altun; Friedmann, J.B.; Luu, Nam Hoai

doi:10.1109/issm.1999.808820

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…Defects that fall onto wafer surface during gate electrode etch process block the poly-silicon etching, inducing bridges between gate lines. 1) As chip size increases and gate length decreases, the yield impact due to a given defect population increases. For this reason, a lot of efforts for defect reduction have been carried out.…”

Section: Introductionmentioning

confidence: 99%

Etch Defect Reduction Using SF₆/O₂ Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process

Mun

Shin

Lee

et al. 2005

Jpn. J. Appl. Phys.

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Since the PAMELA results on the "anomalously" high positron fraction and the lack of antiproton excess in our Galaxy, there has been a tremendous number of studies advocating new types of dark matter, with larger couplings to electrons than to quarks. This raises the question of the production of dark matter particles (and heavy associated coloured states) at LHC. Here, we explore a very simple benchmark dark matter model and show that, in spite of the agreement between the PAMELA antiproton measurements and the expected astrophysical secondary background, there is room for large couplings of a WIMP candidate to heavy quarks. Contrary to what could have been naively anticipated, the PAMELAp/p measurements do not challenge dark matter model building, as far as the quark sector is concerned. A quarkophillic species is therefore not forbidden. Owing to these large couplings, one would expect that a new production channel opens up at the LHC, through quark-quark and quark-gluon interactions. Alas, when the PDF of the quark is taken into account, prospects for a copious production fade away.

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Section: Introductionmentioning

confidence: 99%

Etch Defect Reduction Using SF₆/O₂ Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process

Mun

Shin

Lee

et al. 2005

Jpn. J. Appl. Phys.

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In-Line Defect Reduction From a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing

Guldi

2004

IEEE Trans. Semicond. Manufact.

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"RF-on" polysilicon etch defectivity monitor for manufacturing and process development

Cited by 2 publications

References 5 publications

Etch Defect Reduction Using SF₆/O₂ Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process

Etch Defect Reduction Using SF₆/O₂ Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process

In-Line Defect Reduction From a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing

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"RF-on" polysilicon etch defectivity monitor for manufacturing and process development

Cited by 2 publications

References 5 publications

Etch Defect Reduction Using SF6/O2 Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process

Etch Defect Reduction Using SF6/O2 Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process

In-Line Defect Reduction From a Historical Perspective and Its Implications for Future Integrated Circuit Manufacturing

Contact Info

Product

Resources

About

Etch Defect Reduction Using SF₆/O₂ Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process

Etch Defect Reduction Using SF₆/O₂ Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process