RF Small-Signal and Noise Modeling Including Parameter Extraction of Nanoscale MOSFET From Weak to Strong Inversion

Chalkiadaki, Maria-Anna; Enz, Christian

doi:10.1109/tmtt.2015.2429636

Cited by 38 publications

(26 citation statements)

References 35 publications

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“…Two different commercial bulk CMOS technologies have been investigated, namely a 40 nm [1] and a 28 nm. The simulations have been carried out keeping the parameters shown in Table I constant, where…”

Section: Numerical Results and Comparisonsmentioning

confidence: 99%

“…As pointed out in Section III-B, the bias current I b has been chosen such that A diff = 100 mV for each value of IC and the transistors have been sized accordingly, W /L = I b / 2 IC I spec . The parasitic capacitances, G m and G ds have been extracted from the Y-parameters of the transistors, obtained with a separate S-parameter simulation, as described in [1]. Moreover, the leakage currents I lS and I lD have been evaluated using the DC current through the transistors gate.…”

Section: Numerical Results and Comparisonsmentioning

confidence: 99%

“…1 are replaced by their quasi-static (QS) RF small-signal equivalent circuit in saturation with their noise sources, fully described in [1] [8] [9]. The complete RF model includes: the gate and the bulk resistances, R G and R B , the source/drain access resistances, R S and R D , the parasitic capacitances between gate and source, C GS , gate and drain, C GD , gate and bulk, C GB , source and bulk, C BS , drain and bulk, C DB .…”

Section: B Description Of the Transistor Modelmentioning

confidence: 99%

“…Indeed, even if the metallic gate has become a process option for most recent technology nodes (e.g. 28 nm technology), the gate resistance measured on these devices is still relevant and even greater than in older nodes [1] [2]. Moreover, the gate leakage shot noise contribution has increased mainly due to the shrinking of the gate oxide thickness, although the inclusion of high-k dielectric materials in latest nodes should attenuate this effect.…”

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confidence: 99%

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Linear analysis of phase noise in LC oscillators in deep submicron CMOS technologies

Chicco

Capoccia

Pezzotta

et al. 2017

2017 International Conference on Noise and Fluctuations (ICNF)

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Abstract-This paper investigates the phase noise in LC oscillators with NMOS cross-coupled pair by means of a linear analysis. The latter includes the impact of noise sources that are often neglected, such as gate leakage shot noise, induced gate noise and all terminal access resistances noise. Despite not considering up-conversion of flicker noise, this linear analysis still provides reliable and useful results, demonstrated by means of a detailed comparison between the analytical description and simulations results from a 40 nm and a 28 nm CMOS technology.Index Terms-LC oscillators, phase noise, linear analysis, inversion coefficient I. INTRODUCTIONThe typical architecture of transceivers used in radios relies on frequency synthesizers for generating accurate and low-noise carriers, which are used to up-and down-convert the base-band signal carrying data. Voltage-Controlled-Oscillators (VCO) are one of the key building blocks of frequency synthesizers and they are usually classified in two families: harmonic (i.e. LCbased) and relaxation oscillators (i.e. ring-based). The former category includes the oscillators which are more suited for the aforementioned purpose, since they embed an LC tank to select the target frequency. As a consequence, the output is an almost perfect sinusoid and its phase noise performance is pretty good, compared to the more noisy square wave produced by a ring-oscillator. However, the better output signal quality comes at the price of a larger power consumption.As a matter of fact, due to technology scaling, the impact of parasitic resistances has increased. Indeed, even if the metallic gate has become a process option for most recent technology nodes (e.g. 28 nm technology), the gate resistance measured on these devices is still relevant and even greater than in older nodes [1] [2]. Moreover, the gate leakage shot noise contribution has increased mainly due to the shrinking of the gate oxide thickness, although the inclusion of high-k dielectric materials in latest nodes should attenuate this effect.An analytical derivation of phase noise is carried out including all noise sources, highlighting the transfer function of each of them to the output. The complete expressions come also in a simplified form, in order to provide an insight into possible strategies for noise optimization.The paper is organized as follows. In Section II the description of the circuit and of the transistor model with the noise sources is carried out. Section III details the analysis showing a comparison between analytical and simulated results, followed by conclusions.

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Section: Numerical Results and Comparisonsmentioning

confidence: 99%

Section: Numerical Results and Comparisonsmentioning

confidence: 99%

Section: B Description Of the Transistor Modelmentioning

confidence: 99%

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confidence: 99%

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Linear analysis of phase noise in LC oscillators in deep submicron CMOS technologies

Chicco

Capoccia

Pezzotta

et al. 2017

2017 International Conference on Noise and Fluctuations (ICNF)

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“…For the applications in low noise CMOS RF circuits such as low noise amplifier (LNA), accurate modeling of noise is quite important. In the past decade, HF noise characterization and modeling for bulk and floating body SOI MOSFETs has been widely studied [6][7][8][9][10][11][12][13][14][15], and some modeling methods have been proposed. In [16], the authors proposed a channel segmentation model for accurate channel noise by several independent MOS model.…”

Section: Introductionmentioning

confidence: 99%

A Small-Signal Analysis Based Thermal Noise Modeling Method for Rf Soi Mosfets

Xiang¹,

Huang²,

Liu³

et al. 2017

PIER M

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Abstract-We investigate thermal noise mechanisms and present analytical expressions of the noise power spectral density at high frequencies (HF) in Silicon-on-insulator (SOI) MOSFETs. The developed HF noise model of RF T-gate body contact (TB) SOI MOSFET for 0.13-µm SOI CMOS technology accounts for the mechanisms of 1) channel thermal noise; 2) induced gate noise; 3) substrate resistance noise and 4) gate resistance thermal noise. The extraction method of modeling parameter utilized by Y -parameter analysis on the proposed small-signal equivalent circuit is demonstrated in this paper. Excellent agreement between simulated and measured noise data is obtained at different temperatures.

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