In this paper, we propose a physics-based compact model of the pinned photodiode (PPD) combined with the transfer gate. A set of analytical expressions is derived for the 2-D electrostatic profile, the PPD capacitance, and the charge transfer current. The proposed model relies on the thermionic emission current mechanism, the barrier modulation, and the full-depletion approximation to obtain the charge transfer current. The proposed physics-based model is fully validated with technology computer-aided design simulations, i.e., stationary and optoelectrical simulations. The development of such a compact model for PPD represents an essential step toward the design, simulation, and optimization of PPD-based pixels in CMOS image sensors. Index Terms-Charge transfer, CMOS image sensors (CISs), compact modeling, pinned photodiode (PPD).

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In this article, the impact of the combination of the column-level gain and the correlated multiple sampling (CMS) on the noise of CMOS image sensor (CIS) readout chains is first analyzed. The theory is then validated experimentally with CIS readout chains embedding two different pixels, a variable gain column-level amplifier (CLA) and a passive switched-capacitor (SC) CMS circuit. The noise measurements include photon transfer curves (PTCs) for different gains and pixels and they show reasonably well that CMS reduces the 1/f noise by about 33% for order 8 as expected theoretically.

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Abstract-This work explores the combination of a downscaled technology with in-pixel source-follower (SF) optimization, a high column-level gain and an analog implementation of CorrelatedMultiple-Sampling (CMS) for noise reduction of CIS readout chains. Transient noise simulations show that in the optimal condition of a pMOS SF, a column-level gain equal to 64 and a CMS of order 8, the noise can be reduced to the extremely low value of 0.20 e − rms , with a readout time of 43 μs, demonstrating the possibility of true photoelectron counting for this standard 65 nm process.