RFCMOS Unit Width Optimization Technique

Abstract

In this paper, we demonstrate a unit width ( ) optimization technique based on their unity short-circuit current gain frequency ( ), unilateral power gain frequency ( MAX ), and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the change is different; hence, some tradeoff is required to obtain the optimum value. During the HF noise analysis, a new FOM is proposed to study the effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor's layout and helps to select the optimum for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit's performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.

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