A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-m RFCMOS technology, experimental results in this paper reveal that inductors' core diameters must be adequately large, more than 100 m, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit's operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.

This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasing dependences and by implementing additional noise sources into the small-signal RFCMOS model, accurate HF noise simulation for the transistor can be achieved. Verilog-A is used for the coding of the additional noise sources into the RFCMOS model and the added noise source will compensate the underestimation of the channel thermal noise from the BSIM3v3 core model. Simulated noise circles and the measured noise figures are plotted at other source impedances to show that all the noise parameters are simulated accurately. The biasing and geometry dependences of the measured and simulated noise parameters are presented to demonstrate the scalability of the developed HF noise model. The scalability feature in HF noise model can be implemented into the process design kit (PDK) so that more powerful PDK can be developed for the circuit designers to optimize and simulate their circuit design that requires stringent noise specifications. The accurate noise simulation can ensure better chance of success and reduce the number of tape-out and design cycle time.Index Terms-BSIM3v3, high-frequency (HF) noise model, HF noise modeling, RF MOSFET, RFCMOS, Verilog-A.

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In this paper, we demonstrate a unit width ( ) optimization technique based on their unity short-circuit current gain frequency ( ), unilateral power gain frequency ( MAX ), and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the change is different; hence, some tradeoff is required to obtain the optimum value. During the HF noise analysis, a new FOM is proposed to study the effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor's layout and helps to select the optimum for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit's performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.

Abstract-A scalable and highly accurate RF symmetrical inductor model (with model error of less than 5%) has been developed from more than 100 test structures, enabling device performance versus layout size trade-offs and optimization up to 10 GHz. Large conductor width designs are found to yield good performance for inductors with small inductance values. However, as inductance or frequency increases, interactions between metallization resistive and substrate losses render the use of large widths unfavorable as they consume silicon area and degrade device performance. These findings are particularly important when exploiting the cost-effective silicon-based RF technologies for applications with operating frequencies greater than 2.5 GHz.