Ring-gate MOSFET test structures for measuring surface-charge-layer sheet resistance on high-resistivity-silicon substrates

Abstract

Ring-gate MOSFET test structures have been developed with which a differential measurement technique can be used to accurately determine the surface-charge-layer sheet resistance on high-resistivity-silicon substrates. The difference in substrate properties and influence of special surface passivation techniques that are designed to suppress the otherwise conductive surface channel can thus be monitored and characterized for RF transmission line applications.

Dealing with leakage current in TLM and CTLM structures with vertical junction isolation

“…The perimeter of the outer electrode is fixed to 862 µm. For the sheet resistance extraction procedure see [17]. Right: schematic cross section of the ring structure drawn from the center of inner electrode towards the outer electrode.…”

“…9. Additional information about this type of structure and its application can be found in [17]. Before testing, the wafer is cut into two pieces by notching.…”

Low temperature pure boron layer deposition for Si diode and micromachining applications

“…The Rsh increased as the ring width, L, increases. Due to the curvature of the rings, the Rsh(L) is not linear, and a radial correction factor must be applied [114], where the indices i = 1, ..., 5 refer to each specific test structures in the given set of structures., and Li < Li+1, i < j.…”

Chemical Vapor Deposition of α-Boron Layers on Silicon for Controlled Nanometer-Deep p + n Junction Formation

“…The B layer itself was in contact with pre-fabricated implanted p + plugs, via contact windows, and PVD Al/Si(1%) metallization of both the front and back of the wafer provided electrodes to the n-wafer as well as the p-type regions and gates on the front. The sheet resistance of the B layers was determined by differential electrical measurements on ring-shaped test structures similar to those described by Evseev et al 12 For diode fabrication, we reduced the series resistance by processing p-type wafers with a 0.9 lm n-doped epitaxial layer ($10 16 cm À3 ) on an n + buried layer that was in contact with implanted n + plugs. In some cases the surface doping was increased to a concentration of $10 17 cm À3 by the implanting of phosphorus through a 30 nm-thick thermal oxide.…”