Ring-oscillator-based timing generator for ultralow-power applications

Angelov, Pavel; Nielsen-Lonn, Martin; Alvandpour, Atila

doi:10.1109/norchip.2017.8124969

Cited by 3 publications

(2 citation statements)

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“…Since the timing generator drives many signals with high switching activity, and has to be operated for many cycles for each bias flipping, special consideration has been put on its power efficiency. Therefore, we developed the timing generator which we first presented in a generalized form in [14] and is shown, tailored for the current needs, in Fig. 6.…”

Section: Timing Generationmentioning

confidence: 99%

A Fully Integrated Multilevel Synchronized-Switch-Harvesting-on-Capacitors Interface for Generic PEHs

Angelov

Nielsen-Lonn

2020

IEEE J. Solid-State Circuits

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This paper presents a novel architecture for realizing the synchronized-switch-harvesting-on-capacitors (SSHC) technique used for enhanced energy extraction from piezoelectric transducers. The proposed architecture allows full integration by utilizing the storage capacitor already present in most energy harvesting systems. A promising circuit implementation of the technique, named multilevel synchronized-switch harvesting on capacitors (ML-SSHC), is proposed as well, and its performance is analyzed theoretically. On the basis of that, a fully integrated and power-efficient transistor-level design in 0.18-µm CMOS is presented and fabricated in a prototype chip. When operating at a mechanical excitation frequency of 22 Hz and delivering between 1.51 µW and 4.82 µW, the measured increase in extracted power is 7.01× and 6.71×, respectively, relative to an ideal full-bridge rectifier. While the performance is comparable to the state-of-the-art, this is the first implementation allowing full integration at such low frequencies without posing special requirements on the piezoelectric harvester.

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Section: Timing Generationmentioning

confidence: 99%

A Fully Integrated Multilevel Synchronized-Switch-Harvesting-on-Capacitors Interface for Generic PEHs

Angelov

Nielsen-Lonn

2020

IEEE J. Solid-State Circuits

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“…The traditional NOC consists of a Ring oscillator, NOR gate, and cascaded delay blocks. There are several methods reported for the generation of delay block, which is further used to design the ring oscillator and NOC [4][5][6][7][8][9][10][11][12][13][14]. For low frequency applications, the delay bock should provide more delay.…”

Section: Introductionmentioning

confidence: 99%

Design of efficient delay block for low frequency application

2020

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In recent years researchers have been focusing on the design of low power and small size oscillator for emerging areas of interest such as the internet of things (IoT) and biomedical applications. In this paper a new delay block for ring oscillator is proposed using CMOS inverter cascaded with inverted current starved inverter (CICSI). The designed delay block provides approximately 50% more delay with a smaller number of transistors than the conventionally designed circuits. Furthermore, a ring oscillator and a non-overlapping clock (NOC) generator are designed using it. The designed circuits can be used in switched capacitor (SC) circuits, analog mixed signal circuits to meet the need for low frequency portable biomedical applications. The designed circuits are simulated on Generic 90nm 1.2V Process Design Kit (GPDK90) using Cadence Virtuoso Design Environment. The simulation result shows the delay of the CICSI delay block is 592ps. The ring oscillator using 101 stages of delay block is designed and it is shown that it operates at a frequency of 17MHz with a power consumption of 420?W.

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