RipTide: A Programmable, Energy-Minimal Dataflow Compiler and Architecture

Gobieski, Graham; Ghosh, Souradip; Heule, Marijn J. H.; Mowry, Todd C.; Nowatzki, Tony; Beckmann, Nathan; Lucia, Brandon

doi:10.1109/micro56248.2022.00046

Cited by 21 publications

(2 citation statements)

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“…Special-purpose dataflow architectures find ample use in machine learning accelerators, and were proven useful since the first attempts to accelerate CNNs with fixed-function hardware [38], [39]. Some recent works have attempted to improve the programmability of CGRA-based dataflow systems by increasing their ability to handle complex control-flow [40]. Others propose processors with a tree-like microarchitecture that is specially apt at mapping irregular DAG applications [41].…”

Section: Related Workmentioning

confidence: 99%

Enabling HW-Based Task Scheduling in Large Multicore Architectures

Morais,

Álvarez,

Jiménez-González

et al. 2024

IEEE Trans. Comput.

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Dynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrisically irregular or data-dependent parallelism. The performance of such solutions relies on the ability of the Task Scheduling HW/SW stack to efficiently evaluate dependencies at runtime and schedule work to available cores. Traditional SW-only systems implicate scheduling overheads of around 30K processor cycles per task, which severely limit the (core count, task granularity) combinations that they might adequately handle. Previous work on HW-accelerated Task Scheduling has shown that such systems might support high performance scheduling on processors with up to eight cores, but questions remained regarding the viability of such solutions to support the greater number of cores now frequently found in high-end SMP systems. The present work presents an FPGA-proven, tightly-integrated, Linux-capable, 30-core RISC-V system with hardware accelerated Task Scheduling. We use this implementation to show that HW Task Scheduling can still offer competitive performance at such high core count, and describe how this organization includes hardware and software optimizations that make it even more scalable than previous solutions. Finally, we outline ways in which this architecture could be augmented to overcome inter-core communication bottlenecks, mitigating the cache-degradation effects usually involved in the parallelization of highly optimized serial code.

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Section: Related Workmentioning

confidence: 99%

Enabling HW-Based Task Scheduling in Large Multicore Architectures

Morais,

Álvarez,

Jiménez-González

et al. 2024

IEEE Trans. Comput.

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“…RipTide [30] extends SNAFU using a hardware-software co-design methodology to achieve higher performance and efficiency. The control-flow instructions are handled in the Network on Chip (NoC) to increase the utilization of PEs and the compiler handles the placement and routing considering the control-flow handling on NoC.…”

Section: Related Workmentioning

confidence: 99%

3DRA: Dynamic Data-Driven Reconfigurable Architecture

Lee,

Amornpaisannon,

Diavastos

et al. 2023

IEEE Access

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Specialized accelerators are becoming a standard way to achieve both high-performance and efficient computation. We see this trend extending to all areas of computing, from low-power edgecomputing systems to high-performance processors in datacenters. Reconfigurable architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), attempt to find a balance between performance and energy efficiency by trading off dynamism, flexibility, and programmability. Our goal in this work is to find a new solution that provides the flexibility of traditional CPUs, with the parallelism of a CGRA, to improve overall performance and energy efficiency. Our design, the Dynamic Data-Driven Reconfigurable Architecture (3DRA), is unique, in that it targets both low-latency and highthroughput workloads. This architecture implements a dynamic dataflow execution model that resolves data dependencies at run-time and utilizes non-blocking broadcast communication that reduces transmission latency to a single cycle to achieve high performance and energy efficiency. By employing a dynamic model, 3DRA eliminates costly mapping algorithms during compilation and improves the flexibility and compilation time of traditional CGRAs. The 3DRA architecture achieves up to 731 MIPS/mW, and it improves performance by up to 4.43x compared to the current state-of-the-art CGRA-based accelerators.

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