RISC-V Based Safety System-on-Chip with Hardware Comparator

Abstract

In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility.

Safety-Related Computerized Embedded Systems With Heterogenous Redundancy

“…The company has developed four RISCV cores that will be used in a variety of Western Digital products shortly (RISC-V International 2022). Additionally, a modified SweRV EH1 from Hahn et al in 2022(Hahn et al 2022) was selected and altered to meet this design's requirement where the ethernet module is eliminated from the design to be added in the future based on AXI ethernet lite provided by Xilinx Vivado. A secondary AXI (Advanced eXtensible Interface) UART (Universal asynchronous receiver-transmitter) is added for internal communication, and the final RISCV architecture is shown in figure 3.…”