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In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility.

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Compressed air systems are essential components in various industrial and everyday applications. The efficiency of these systems is very important due to their role in the energy consumption of industrial plants. To increase efficiency, a new concept for compressed air compressors based on Industry 4.0 is presented. Due to the aggressive environmental conditions in which the compressed air compressors operate, a new design of a SoC with high availability based on 1oo2 redundancy architecture is developed.