Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues

Reddi, Vijay Janapa; Pan, David Z.; Nassif, Sani R.; Bowman, Keith

doi:10.1109/aspdac.2012.6165064

Cited by 11 publications

(10 citation statements)

References 75 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One mitigation technique [18] aims at effectively confronting this type of variability challenge through the collaboration of hardware with software. Although the resilient circuits ensure correct system operation within the presence of dynamic variations, a hardware-only solution is purely reactive.…”

Section: A Impact Of Supply Voltage (Vdd)mentioning

confidence: 99%

“…Allowing software, such as the operating system or some form of runtime layer, to monitor the recovery cycles in a resilient hardware might enable a more efficient system design by anticipating future events based on the workload. Recent experimental results [18] show that the occurrence of Vdd drops varies widely across the different programs. By giving software the capability to monitor recovery cycles in the resilient hardware, we can track the optimum F clk setting for each workload, store these values, and then reuse this information during subsequent executions.…”

Section: A Impact Of Supply Voltage (Vdd)mentioning

confidence: 99%

“…By giving software the capability to monitor recovery cycles in the resilient hardware, we can track the optimum F clk setting for each workload, store these values, and then reuse this information during subsequent executions. In this way, software can predict the optimal F clk setting based on previous measurements to enhance the performance and energy [18]. This is discussed further in Section VII.…”

Section: A Impact Of Supply Voltage (Vdd)mentioning

confidence: 99%

“…1) is the conventional choice for most on-chip memory designs. We do not change the circuit topology from the standard six-transistor cell because of previous studies discouraging this [17], [18]. With power applied, SRAM provides permanent data storage.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield

2014

View full text Add to dashboard Cite

Effectively confronting device and circuit parameter variations to maintain or improve the design of high performance and energy efficient systems while satisfying historical standards for reliability and lower costs is increasingly challenging with the scaling of technology. In this paper, we develop methods for robust and resilient six-transistor-cell static random access memory (6T-SRAM) designs that mitigate the effects of device and circuit parameter variations. Our interdisciplinary effort involves: 1) using our own recently developed VAR-TX model [1] to illustrate the impact of interdie (also known as die-to-die, D2D) and intradie (also know as within-die, WID) process and operation variations-namely threshold voltage (Vth), gate length (L), and supply voltage (Vdd)-on future different 16-nm architectures and 2) using modified versions of other well-received models to illustrate the impact of variability due to temperature, negative bias temperature instability, aging, and so forth, on existing and next-generation technology nodes. Our goal in combining modeling techniques is to help minimize all major types of variability and to consequently predict and optimize speed and yield for the next generation 6T-SRAMs. aging, optimum architecture, reliability, type of variations, variability, yield. INDEX TERMS

show abstract

Section: A Impact Of Supply Voltage (Vdd)mentioning

confidence: 99%

Section: A Impact Of Supply Voltage (Vdd)mentioning

confidence: 99%

Section: A Impact Of Supply Voltage (Vdd)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield

2014

View full text Add to dashboard Cite

show abstract

“…Process parameter excursions are modeled as circuit parameter perturbations and these are called "parametric faults". They are caused by process parameter excursions at device and interconnect levels [1]. Parametric faults became more important with increased scaling, and variations of the threshold voltage, V th , and effective channel length, l eff , in transistors are the major reasons that contribute toward failure of analog circuits [2].…”

Section: Introductionmentioning

confidence: 99%

Scalable and efficient analog parametric fault identification

Yelten

Natarajan

Xue

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in largescale analog circuits with a constrained simulation budget. Experiment results on two circuits from a serial IO interface demonstrate the effectiveness of the methodology. The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlobased approach for identical computational budget, particularly for cases involving significant process variations. Keywords-test coverage; within-die variations; parametric faults; process variations; analog circuits; design for test.I.

show abstract