Robust FinFET SRAM design based on dynamic back-gate voltage adjustment

Ebrahimi, Behzad; Afzali-Kusha, Ali; Mahmoodi, Hamid

doi:10.1016/j.microrel.2014.04.015

Cited by 17 publications

(13 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, in order to validate the reliability of a SRAM as the building block, the proposed cell is used in designing a SRAM block with 8 cells in each row and 128 cells in each column similar to the block in [6]. The arranged array is driven by four-stage inverter chains to obtain the delay and power consumption in a real situation.…”

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Moghaddam

Timarchi

Moaiyeri

et al. 2015

Circuits Syst Signal Process

View full text Add to dashboard Cite

This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body-source voltage dynamically. Proper usage of low-threshold voltage (L-V t ) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power-delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.

show abstract

Section: Simulation Results and Comparisonsmentioning

confidence: 99%

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Moghaddam

Timarchi

Moaiyeri

et al. 2015

Circuits Syst Signal Process

View full text Add to dashboard Cite

show abstract

“…Ultra scaled devices with better electrical characteristics demand novel device over conventional MOSFET. Therefore SRAM research is turning around FinFET based design [3].…”

Section: Introductionmentioning

confidence: 99%

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

Yadav

Jain

Pattanaik

et al. 2015

Microelectronics Reliability

View full text Add to dashboard Cite

“…The same requirement exists for pull up and pull down transistors in main body for read and write operations [7]. Several recent papers have optimized SRAM cells for read, write or hold characteristics while minimizing the overhead in other modes without considering feasibility and reliability issues [8,9]. Other efforts have biased PFET back-gates to control the threshold voltage and NBTI degradation [10].…”

Section: Introductionmentioning

confidence: 99%

“…Due to PFET back-gate biasing in read and hold modes, the cell has high NBTI degradation and reliability issues, which is not considered. On similar lines, in the design in [9], both PFET back gates are biased to '1' in hold mode for decreasing static power. Back-gate voltages are optimized during read operation for achieving maximal read SNM.…”

Section: Introductionmentioning

confidence: 99%

“…Further, due to supply voltage variation and voltage scaling features in modern caches, the effective voltages over cell frequently change, thereby altering the optimum back gate voltage dynamically. Further, both cells ( [8] and [9]) are controlled with high external voltage, which increases intermediate node activity and reduces cache stability. In summary, prior cell designs only achieve improvements in one or two cell characteristics, while degrading other parameters.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hierarchical design of robust and low data dependent FinFET based SRAM array

Imani

Patil

Rosing

2015

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)

View full text Add to dashboard Cite

This paper proposes a new FinFET based SRAM cell and a cache architecture that efficiently exploits our SRAM cell for low-power and robust memory design. Our cache architecture uses invert coding scheme to encode the input data of a word line by taking into account the data composition. Based on the new data distribution, we propose two new asymmetric SRAM cells (AABG and ADWL) utilizing adaptive back-gate feedback that significantly improve cache power consumption and reliability, and provide higher performance in state-of-theart SRAM caches. The results show that the AABG cell is a good candidate for robust and low power caches, while the ADWLbased SRAM cache is low power and high performance cache. The simulations are performed on SPEC CPU 2006 benchmarks with GEM5 and HSPICE in 20nm independent gate FinFET technology. The results show that the proposed AABG (ADWL)-based cache improves static and dynamic power by at least 13% and 35% (17% and 12%) respectively, compared to other stateof-the-art cells, while guaranteeing 2.7X (1.98X) lower NBTI degradation with less than 1.5% area overhead.

show abstract

Robust FinFET SRAM design based on dynamic back-gate voltage adjustment

Cited by 17 publications

References 20 publications

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

Hierarchical design of robust and low data dependent FinFET based SRAM array

Contact Info

Product

Resources

About