An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Moghaddam, Majid; Timarchi, Somayeh; Moaiyeri, Mohammad Hossein; Eshghi, Mohammad

doi:10.1007/s00034-015-0119-0

Cited by 46 publications

(8 citation statements)

References 17 publications

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“…The 9T cell [17] is based on suppressing the draininduced barrier lowering (DIBL) effect and controlling the body source voltage dynamically to improve the read and write margin as well as to improve the leakage power of the The threshold voltage of a short-channel device is dependent on drain to source voltage due to the DIBL effect and the body effect through body to source voltage BS V [6]:…”

Section: T Sram Using Threshold Voltage Techniquesmentioning

confidence: 99%

“…In [16] cell breaks the feedback loop of the cell during the read operation to guarantee the stability of stored data. In [17], a suitable read operation is provided by suppressing the draininduced barrier lowering effect and controlling the bodysource voltage dynamically. Proper usage of low-threshold voltage transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Vishvakarma

Reniwal

Khuswah

et al. 2015

2015 IEEE International Symposium on Nanoelectronic and Information Systems

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The importance of embedded memory in contemporary multi-core processors and system-on-chip (SoC) for wearable electronics and IoT applications is growing. Intensive data processing in such processors and SoCs necessitates larger on-chip, energy-efficient static random access memory (SRAM). However, there are several challenges associated with low-voltage SRAMs. In this paper we have discussed the major hurdles at technology front for low power and robust SRAM design. We have discussed the different circuit techniques to mitigate these severe reliability concerns for embedded SRAM. Furthermore, this paper presented the recent development in embedded memory technology targeted to efficient computation. We have analyzed the effect of various device sizing on memory stability. The novel current mode circuit is also presented for high speed, offset tolerant SRAM sense amplifier. The FinFET memory design is explored to reduce the external manifestation of device mismatch on SRAM stability and memory yield.Keywords-Current Latch Sense Amplifier, Offset, SRAM, inter die variations, intra die variations.

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Section: T Sram Using Threshold Voltage Techniquesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Vishvakarma

Reniwal

Khuswah

et al. 2015

2015 IEEE International Symposium on Nanoelectronic and Information Systems

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show abstract

“…However, any effective strategy to improve the write ability was absent in this solution. In Moghaddam et al, 14 a 9T cell was proposed that is based on the threshold voltage variation technique, where the dynamic threshold voltage (V TH ) effect and drain-induced barrier lowering (DIBL) concepts were implemented to suppress the leakage issues. A provision to reduce the leakage power was also incorporated whereby the stacking devices in each of the inverter.…”

Section: Introductionmentioning

confidence: 99%

“…But it required the use of wider access devices for improved write ability, and therefore, results in the area overhead. In Moghaddam et al, 14 a 9T cell was proposed that is based on the threshold voltage variation technique, where the dynamic threshold voltage (V TH ) effect and drain-induced barrier lowering (DIBL) concepts were implemented to suppress the leakage issues. Wang et al 15 proposed a method for energy efficient SRAM cell by the strategic use of multi-V TH devices.…”

Section: Introductionmentioning

confidence: 99%

A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes

Sharma

Vishvakarma

Chouhan

et al. 2018

Circuit Theory & Apps

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In this work, a data-dependent feedback-cutting-based bit-interleaved 12T static random access memory (SRAM) cell is proposed, which enhances the write margin in terms of write trip point (WTP) and write static noise margin (WSNM) by 2.14× and 8.99× whereas read stability in terms of dynamic read noise margin (DRNM) and read static noise margin (RSNM) by 1.06× and 2.6 ×, respectively, for 0.4 V when compared with a conventional 6T SRAM cell. The standby power has also been reduced to 0.93× with an area overhead of 1.49× as that of 6T. Monte Carlo simulation results show that the proposed cell offers a robust write margin when compared with the state-of-the-art memory cells available in the literature. An analytical model of WSNM for 12T operating in subthreshold region is also proposed, which has been verified using the simulation results.Finally, a small SRAM macro along with its independent memory controller has been designed. KEYWORDS circuit design, low-power, SRAM, stability, write ability 2314

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“…In [35], cell breaks the feedback loop of the cell during the read operation to guarantee the stability of stored data. In [36], a suitable read operation is provided by suppressing the drain-induced barrier lowering (DIBL) effect and controlling the body-source voltage dynamically. Proper usage of low-threshold voltage transistors in the SRAM design helps to reduce the read access time and enhance the reliability in the subthreshold region.…”

mentioning

confidence: 99%

Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Singh¹,

Vishvakarma²

2017

Preprint

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An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in subthreshold regime which has low power consumption. Therefore, to improve power consumption along with better cell stability, a power gated 10T SRAM is presented. The proposed cell uses a power gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature (PVT) conditions. The proposed SRAM shows better results in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write-ability or write trip point (WTP), read-write energy and dynamic read margin (DRM). Further, these parameters are observed at 8-Kilo bit (Kb) and compared with already existing SRAM architectures. It is observed that the leakage power is reduced by 1/81×, 1/75× of the conventional 6T (C6T) SRAM and read decoupled 8T (RD8T) SRAM, respectively at 300mV VDD. On the contrary, RSNM, WSNM, WTP and DRM values are improved by 3×, 2×, 11.11% and 31.8% as compared to C6T SRAM, respectively. Similarly, proposed 10T has 1.48×, 25% and 9.75% better RSNM, WSNM and WTP values as compared to RD8T SRAM, respectively at 300mV VDD.Keywords: power gating; read decoupling; read-write static noise margin; dynamic noise margin; read-write energy; schmitt trigger; leakage power. IntroductionThe massive constrain headed for internet of things (IoT) devices has led to developments of ultra-low power (ULP) systemson-chip (SoCs) that are capable of operating in sub-threshold voltages [1,2]. One way to guarantee low power and energy consumption is to scale down the supply voltage to the sub-threshold region [3]. However, the reduced on-to-off current ratio (I ON /I OFF ) and the exponential dependence of the current on the threshold voltage (V th ) in the sub-threshold region introduces many challenges especially in rationed circuits such as the traditional 6T static random access memory (SRAM) bit-cell. Since, conventional non-volatile memories consume higher read and write power, the scaling of supply voltages and the techniques to reduce leakage at sub-threshold voltages needed. However, the low cell stability is also one of the factor which defy conventional SRAM architecture to not to work at sub-threshold region [4].However, due to rapid growth of internet market through all over the world, Internet of Things (IoT) brings connectivity, communication, and data gathering to existing devices. IoT includes countless devices connected and communicated with each other to enrich the present lifestyle, and its applicabi...

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An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Cited by 46 publications

References 17 publications

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

A write‐improved low‐power 12T SRAM cell for wearable wireless sensor nodes

Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

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