Robustness of Cascode GaN HEMTs in Unclamped Inductive Switching

Stability, Reliability, and Robustness of GaN Power Devices: A Review

“…In the withstand process, the primary electrical failure is related to the overvoltage margin of the device, i.e., the dynamic breakdown voltage [41]. This BV in the transient switching could be different from the static BV measured through the quasi-static I-V sweep on the curve tracer [22], [41], [172], [173].…”

“…Overall, these two topologies allow for the use of D-mode HEMT, which usually has a simpler gate stack in comparison to the HD-GIT and SP-HEMT [26]. However, the inclusion of multiple chips in the package brings additional driving challenges, as well as the introduction of new failure and instability mechanisms that could be triggered and coupled between the multiple chips [22]. These challenges will be elaborated in the later sections.…”

“…Finally, the origin of C OSS loss in GaN HEMTs is still contentious [108], [112], [115], [116], while a consensus is reached that the carrier trapping/de-trapping induced C OSS hysteresis is a key root cause. However, the location, time constant, energy level, and physical origins of the relevant traps remain unclear [112]. The leakage current in the epitaxial structure [108] and the resonance on the Si substrate [116] have been reported to contribute to the COSS loss.…”

“…In parallel to understanding its origin and mitigation from device perspectives, an immediate need for applications is to provide such information in the device datasheet and the relevant models in the device application note. To facilitate this to happen soon, a widely accepted characterization method is preferable, which should ideally involve the device ON-and OFF-states and best represents the device's steady-state switching in converters [111], [112].…”

“…Additionally, the added inductance to the bond wires between the switches and the Si avalanche can also cause an increase in the internal switching losses [131]. To minimize the interconnection induced loss, the latest generation of commercial Cascode GaN HEMTs eliminate the internal bond wires between the two chips by directly stacking the Si chip onto the source pad of GaN HEMT [22]. Whereas, in some extreme instances, false turn-ON events can occur [132], and short-circuit oscillations can cause catastrophic failures [133].…”