Plasma etching is an enabling technology in nano optic, nanoelectronic devices, nano electro mechanical systems (NEMS) and nanoresolution templates for nano imprint lithography (NIL). With shrinkage, one must overcome significant challenges to meet the stringent profile and CD goals necessary for nanoscale applications. Using the example of Si nanoimprint template fabrication, we show how ion/sidewall/mask interactions can dominate feature profile evolution at the nanoscale and what to look for successful pattern transfer. Gas chopping or multiplexed etching, generally used for deep silicon etching, is often avoided at the nanoscale due to unacceptable undercut and sidewall scalloping. We demonstrate a multiplexed etching process in silicon with sub-5 nm amplitude scallops which is well suited for NEMS and nano optics applications and which reduces the deleterious role of ion/sidewall/mask interactions at the nanoscale.