Role of Through Silicon Via in 3D Integration: Impact on Delay and Power

Abstract

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32[Formula: see text]nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32[Formula: see text]nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20[Formula: see text]GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

Effect of Polymer Liners in Different Via Shapes: Impact on Crosstalk Induced Delay

“…A cylindrical TSV is advantageous over the square, coaxial, and tapered TSVs due to its uniform structure, high breakdown voltage, and simplicity of electrical modelling. At low frequencies, it also outperforms other TSV structures in terms of heat dissipation [5]. However, the cylindrical TSV demonstrates a significant worst-case crosstalk induced delay and less conductivity compared to the other shapes due to more footprint area [5].…”

“…At low frequencies, it also outperforms other TSV structures in terms of heat dissipation [5]. However, the cylindrical TSV demonstrates a significant worst-case crosstalk induced delay and less conductivity compared to the other shapes due to more footprint area [5]. In this regard, a coaxial shaped TSV can be considered in terms of less footprint area and improved noise performance.…”

“…However, as per the fabrication house, the formation of this guard ring between the inner and outer conducting filler is still a challenging task. Therefore, a tapered TSV is preferred due to its straightforward fabrication, less footprint area, balanced power and thermal distribution in 3D ICs [5].…”

An analysis of the eddy effect in through-silicon vias based on Cu and CNT bundles: the impact on crosstalk and power

“…Thus eddy resistance comes into the existence in the silicon substrate, neighboring TSVs, and depletion regions due to the flow of eddy current. In general, most of the state-ofthe art experimental evidences [11][12][13][14][15][16][17][18][19][20] describes an equivalent RLGC model of the cylindrical-shaped TSV without considering the eddy effect at high frequencies. Previously, Khalil et al [11] demonstrated an analytical model of Cu-based TSV that depends on its physical parameters.…”

“…Although a comprehensive analysis has been performed for transmission coefficient and high-frequency impedance considering TSV design parameters but the impact of the eddy effect is restricted only to the silicon substrate. In recent, the researchers in [20] have demonstrated the crosstalk induced delay and power dissipation for cylindrical, tapered, square, and annular shaped TSVs considering the skin effect at high frequency. The authors proposed an electrical equivalent model of metal-insulator-semiconductor (MIS) and metalsemiconductor (MES) based on different TSV shapes to analyze the power delay product (PDP).…”