The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32[Formula: see text]nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32[Formula: see text]nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20[Formula: see text]GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

This paper presents the first realistic and holistic approach to exhibit compact resistance-inductance-capacitanceconductance (RLCG) model for (Carbon nanotube) CNT and Cu based different shaped through-silicon vias (TSVs) in 3-D ICs. The model primarily comprises the effect of bump, inter-metal dielectric, and eddy currents. Using the proposed model, a mathematical formulation for the coaxial, cylindrical, and tapered based via parasitics are derived using the concept of partial inductance, sectioning via laterally into infinitesimally thin slices and triangular inter-tube assemblage, respectively. The analytical model is validated against a fabrication based experimental results and subsequently employed for crosstalk induced delay, peak noise, and power losses analysis. Additionally, for the further validation, the S parameter for the Pi-based model is derived, and compared with an electromagnetic simulator to benchmark the proposed model. The tremendous consistency between the analytical and EM simulation based results further evidences the validity of the proposed model. Encouragingly, a significant improvement in the power losses, crosstalk, and peak noise can be observed using the CNT-based tapered TSV compared to the Cu-based via structures. Additionally, it is shown that the irrespective of via height, the average crosstalk induced delay, peak noise, signal transmission, and reflection loss of the TSV with tapered shaped 15-shell CNT bundle is reduced by 22.82%, 27.80%, 47.63%, and 33.71%, respectively compared to the Cu. KeywordsCrosstalk-induced delay • Eddy effect • Single-Walled Carbon nanotube (CNT) • 3-D IC • Mean-time-to-failure (MTTF) • resistance-inductance-capacitance-conductance (RLCG) model • Through-silicon via (TSV).

No abstract

No abstract

No abstract