2022
DOI: 10.1109/ojnano.2022.3221815
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Performance Analysis of Bump in Tapered TSV: Impact on Crosstalk and Power Loss

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Cited by 5 publications
(2 citation statements)
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“…The 3D integration provides large bandwidth, small foot print, reduced form factor and lower interconnect complexity over the two dimensional integration technologies. [9][10][11] The 3D technology attracted the semiconductor design engineers as it offers tremendous platform to attain more than Moore law. This brings heterogeneous materials such as Silicon (Si), II-V semiconductor and graphene, and technologies such as memories, optoelectronics, and logics on single chip.…”
mentioning
confidence: 99%
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“…The 3D integration provides large bandwidth, small foot print, reduced form factor and lower interconnect complexity over the two dimensional integration technologies. [9][10][11] The 3D technology attracted the semiconductor design engineers as it offers tremendous platform to attain more than Moore law. This brings heterogeneous materials such as Silicon (Si), II-V semiconductor and graphene, and technologies such as memories, optoelectronics, and logics on single chip.…”
mentioning
confidence: 99%
“…The TSVs plays a major role by supplying the current. 9,12 The TSVs are metal liners surrounded with the dielectric liner that is placed in silicon. The performances of 3D IC are depends on the metal liner utilized in the TSVs.…”
mentioning
confidence: 99%