Room temperature ALD oxide liner for TSV applications

Zhang, Dingyou; Smith, Daniel M.; Lundeen, David; Kakita, Shinichiro; England, Luke

doi:10.1109/ectc.2015.7159572

Cited by 8 publications

(4 citation statements)

References 18 publications

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“…As a result, it was indicated, for the first time, that depth-dependent interface states existed in the TSV liner, which enhances the noise propagation among stacked chips. For high reliability mixed-signal 3D-IC, novel technologies such as an atomic layer process, novel barrier technologies and a polymer liner process are necessary to improve step-coverage and decrease the trap density around the TSV liner [15]- [22].…”

Section: Discussionmentioning

confidence: 99%

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Kino

Fukusima

Tanaka

2019

IEEE J. Electron Devices Soc.

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Mixed-signal 3D-ICs have a stacked structure of digital and analog circuit chips. In this study, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC. The noise propagation via through-silicon vias (TSVs) was measured, with a ring-oscillator as a noise source. For a comprehensive investigation, TSV-liner interface states were evaluated along the depth direction using unique multiwell-structured TSVs and a charge-pumping method. It was considered that the interface traps and nonconformal thickness of the TSV liner increased the noise propagation among stacked chips.INDEX TERMS 3D IC, through-silicon vias, charge pumping method, interface trap.

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Section: Discussionmentioning

confidence: 99%

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Kino

Fukusima

Tanaka

2019

IEEE J. Electron Devices Soc.

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“…The MIV-devices are modeled using Sentaurus Structure Editor tool where the substrate is n-type with Arsenic (As) doping concentration of 10 17 cm −3 The region around MIV is doped with Boron (B) using Gaussian profile concentration with a peak concentration of 10 19 cm −3 to form source terminal of the MIVcapacitor. The liner around MIV is assumed to be 1 nm considering the scaling between the TSV to MIV as discussed in [23,24]. The substrate terminal is formed with a highly doped n+ region on the substrate to provide substrate biasing.…”

Section: Miv-capacitormentioning

confidence: 99%

Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC

Vemuri,

Tida

2024

IEEE Access

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Transistor-level monolithic three-dimensional integrated circuit (M3D-IC) technology potential is compromised with the silicon footprint overhead caused by metal inter-layer via (MIV). To address this issue, we present a dual-purpose MIV-device utilization where MIV serves two purposes: 1. interconnect and 2. device terminal. A detailed study of the proposed MIV-devices specifically MIV-capacitor and MIVtransistor is performed and a strategy to extract level-3 Spice models is presented in this paper. Simulation results suggest that the basic logic gates designed with the opportunistic utilization of MIV-devices reduce the substrate utilization by up to 22% compared with the conventional transistor-level implementation in M3D-IC technology.

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“…However, although the conformality of the deposition is very good, the low deposition rate makes the ALD process not cost-effective. 15 More recently, Vitiello and Piallat have developed a deposition method called Fast Atomic Sequential Technology, which is a combination of CVD with atomic layer deposition pulsing capability. 16 This approach allows us to compensate for the low deposition rate of (PE)ALD and presents good conformality performances by combining ALD film performances at the deposition rate of CVD.…”

Section: ■ Introductionmentioning

confidence: 99%

“…However, one drawback is the poor dielectric properties of the deposited film at temperatures below 400 °C. , Previous works have combined PECVD with SACVD, but the obtained films still exhibit insufficient electrical characteristics. , Besides, atomic layer deposition (ALD) has been investigated as an alternative method for the deposition of an insulating layer for TSVs. However, although the conformality of the deposition is very good, the low deposition rate makes the ALD process not cost-effective . More recently, Vitiello and Piallat have developed a deposition method called Fast Atomic Sequential Technology, which is a combination of CVD with atomic layer deposition pulsing capability .…”

Section: Introductionmentioning

confidence: 99%

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD

Jousseaume,

Guerin,

Ichiki

et al. 2024

ACS Appl. Mater. Interfaces

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In microelectronics, one of the main 3D integration strategies consists of vertically stacking and electrically connecting various functional chips using through-silicon vias (TSVs). For the fabrication of the TSVs, one of the challenges is to conformally deposit a low dielectric constant insulator thin film at the surface of the silicon. To date, there is no universal technique that can address all types of TSV integration schemes, especially in the case requiring a low deposition temperature. In this work, an organosilicate polymer deposited by initiated chemical vapor deposition (iCVD) was developed and integrated as an insulating layer for TSVs. Process studies have shown that poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (P(V 3 D 3 )) can present good conformality on high aspect ratio features by increasing the substrate temperature up to 100 °C. The trade-off is a moderate deposition rate. The thermal stability of the polymer has been investigated, and we show that a thermal annealing at 400 °C (with or without ultraviolet exposure) allows the stabilization of the dielectric films by removing residual oligomers. Then, P(V 3 D 3 ) was integrated in high aspect ratio TSV (10 × 100 μm) on 300 mm silicon wafers using a standard integration flow for TSV metallization. Functional devices were successfully fabricated (including daisy chains of 754 TSVs) and electrically characterized. Our work shows that the metallization barrier should be carefully selected to eliminate the appearance of voids at the top corner of the TSV after the Cu annealing step. Moreover, an appropriate integration process should be used to avoid the appearance of cohesive cracks in the liner. This work constitutes a first proof of concept of the use of an iCVD polymer in a quasi-industrial microelectronic environment. It also highlights the benefit of iCVD as a promising technique to deposit conformal dielectric thin films in a microelectronic pilot line environment.

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Room temperature ALD oxide liner for TSV applications

Cited by 8 publications

References 18 publications

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD

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