Room-temperature side-gate-induced current modulation in a magnetic tunnel junction with an oxide-semiconductor barrier for vertical spin MOSFET operation

Kanaki, Toshiki; Matsumoto, Shin; Narayananellore, Sai Krishna; Saito, H.; Iwasa, Yoshihiro; Tanaka, Masaaki; Ohya, Shinobu

doi:10.7567/1882-0786/aafed6

Cited by 7 publications

(7 citation statements)

References 30 publications

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“…, exhibited greater MR ratios (60% for GaAs at 3.5 K 20) and 37% for GaO x at RT 22) ). It is also notable that a lateral spin valve made of a two-dimensional electron gas formed in a GaAs/AlGaAs heterointerface exhibited large MR ratio of 80% at 1.6 K. 23) While the on/off ratio of source-drain current (which is a pivotal parameter in spin MOSFET operations) is greater than 10 3 (=100,000%) at RT in Si-based spin MOSFETs, 13,14,17) which is superior to those in GaAs-(125% at 3.8 K 21) ) and GaO x -based spin MOSFETs (10% at RT 22) ), there is much room for improvement to augment the MR ratio in Si-based spin MOSFETs to realize reconfigurable logic circuits. 3) Among a number of approaches to augment the MR ratio of Si-LSVs, we shed light on the resistance-area product (RA) of Fe/MgO/n + -Si contacts and the momentum relaxation time (τ e ) in the n-Si channel.…”

Section: )mentioning

confidence: 98%

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Over 1% magnetoresistance ratio at room temperature in non-degenerate silicon-based lateral spin valves

Koike

Lee

Ohshima

et al. 2020

Appl. Phys. Express

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To augment the magnetoresistance (MR) ratio of n-type non-degenerate Si-based lateral spin valves (Si-LSVs), we modify the doping profile in the Si layer and introduce a larger local strain into the Si channel by changing a capping insulator. The highest MR ratio of 1.4% is achieved in the Si-LSVs through these improvements, with significant roles played by a reduction in the resistance-area product of the ferromagnetic contacts and an enhancement of the momentum relaxation time in the Si channel.

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Section: )mentioning

confidence: 98%

“…However, the low magnetoresistance (MR) ratio of Si-based spin transport devices hampers further progress on Si spintronics. In fact, the MR ratio of Si-based spin MOSFETs remains less than 0.5% at RT, [12][13][14][15][16][17] although similar spin MOSFETs using the other materials, for example GaAs 20,21) and GaO x…”

mentioning

confidence: 99%

Over 1% magnetoresistance ratio at room temperature in non-degenerate silicon-based lateral spin valves

Koike

Lee

Ohshima

et al. 2020

Appl. Phys. Express

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“…Among the spin devices proposed thus far, spin transistors are expected to be applied to nonvolatile electronic circuits as post‐Moore devices. [ 3–12 ] Notably, a spin metal–oxide–semiconductor field‐effect transistor (spin MOSFET), [ 13 ] in which ferromagnetic (FM) electrodes replace the drain and source electrodes of conventional MOSFETs, is particularly promising. This device is expected to operate with very short channel lengths, similar to state‐of‐the‐art MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Giant Spin‐Valve Effect in Planar Spin Devices Using an Artificially Implemented Nanolength Mott‐Insulator Region

et al. 2023

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Developing technology to realize oxide-based nanoscale planar integrated circuits is in high demand for next-generation multifunctional electronics. Oxide circuits can have a variety of unique functions, including ferromagnetism, ferroelectricity, multiferroicity, superconductivity, and mechanical flexibility. In particular, for spin-transistor applications, the wide tunability of the physical properties due to the presence of multiple oxide phases is valuable for precise conductivity matching between the channel and ferromagnetic electrodes. This feature is essential for realistic spin-transistor operations. Here, a substantially large magnetoresistance (MR) ratio of up to ≈140% is demonstrated for planar-type (La,Sr)MnO 3 (LSMO)-based spin-valve devices. This MR ratio is 10-100 times larger than the best values obtained for semiconductor-based planar devices, which have been studied over the past three decades. This structure is prepared by implementing an artificial nanolength Mott-insulator barrier region using the phase transition of metallic LSMO. The barrier height of the Mott-insulator region is only 55 meV, which enables the large MR ratio. Furthermore, a successful current modulation, which is a fundamental functionality for spin transistors, is shown. These results open up a new avenue for realizing oxide planar circuits with unique functionalities that conventional semiconductors cannot achieve.

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“…Printing or coating processes can provide the low-cost fabrication of flexible, large-area electronic devices, compared to MEMS 29,30 or semiconductor processes. 31,32 Air-gap structures are often found in MEMS touch sensors 33,34 and they are designed to sense external force by detecting deformation of a component placed on the air-gap. In general, air-gap structures are fabricated by the etching process in MEMS fabrication.…”

Section: ■ Introductionmentioning

confidence: 99%

“…In addition, coating methods, such as slot-die coating − and spin-coating, , are also used. Printing or coating processes can provide the low-cost fabrication of flexible, large-area electronic devices, compared to MEMS , or semiconductor processes. , …”

Section: Introductionmentioning

confidence: 99%

Fabrication and Characterization of Roll-to-Roll-Coated Cantilever-Structured Touch Sensors

Lee

2020

ACS Appl. Mater. Interfaces

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It is common in the field of printed electronics that polydimethylsiloxane (PDMS) be used as a dielectric layer for capacitive sensors because of its high elasticity and restoration force. However, capacitive sensors with the PDMS dielectric layer have a lower sensitivity than those with an air-gap structure that has been fabricated by the conventional micro-electromechanical system (MEMS) process. This paper presents a productive method for fabricating air-gap structures for touch sensors by roll-to-roll slot-die coating. The air-gap is formed by coating and removing a sacrificial layer. Cantilever-structured capacitive touch sensors with an air-gap are fabricated as follows: First, the bottom electrode, the dielectric layer, and the poly(vinyl alcohol) (PVA) sacrificial layer are roll-to-roll slot-die-coated on a flexible substrate. In addition, the spacer layer is spin-coated. On the sacrificial and spacer layers, the top electrode and structural layer are formed by spin-coating. Then, the air-gap and cantilever structure are made by removing the sacrificial layer in water. The cantilever-structured sensor samples are examined in terms of sensitivity, hysteresis, and repeatability. In particular, the electrical performance of the samples is compared to those with the PDMS dielectric layer. Experimental results show that the cantilever-structured sensor samples have significantly higher sensitivity compared to those with the PDMS dielectric layer.

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Room-temperature side-gate-induced current modulation in a magnetic tunnel junction with an oxide-semiconductor barrier for vertical spin MOSFET operation

Cited by 7 publications

References 30 publications

Over 1% magnetoresistance ratio at room temperature in non-degenerate silicon-based lateral spin valves

Over 1% magnetoresistance ratio at room temperature in non-degenerate silicon-based lateral spin valves

Giant Spin‐Valve Effect in Planar Spin Devices Using an Artificially Implemented Nanolength Mott‐Insulator Region

Fabrication and Characterization of Roll-to-Roll-Coated Cantilever-Structured Touch Sensors

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