Rothko: a three-dimensional FPGA

Abstract

ACHIEVING NEW LEVELS of integration and utilization in field-programmable logic requires new FPGA architectures. Problems with existing architectures include low resource utilization, routing congestion, high interconnect delay, and insufficient I/O connections. At Northeastern University, we have developed a novel three-dimensional FPGA architecture called Rothko, aimed at solving some of these problems. The technology underlying Rothko allows designers to stack two-dimensional CMOS circuits to build 3D VLSI structures. Vertical metal interconnects between layers (interlayer vias) can be placed anywhere on the chip. Overcoming problems One of the main obstacles to mapping large designs onto existing FPGA architectures is routing congestion. Although in current commercial FPGAs, routing resources take up a major part of the chip, implementing complex designs is often difficult due to a lack of routing resources. Routing resources in FPGAs are more expensive than in ASICs because FPGAs require programmable interconnect to maintain a flexible architecture. Programmable interconnect needs more area than fixed routing and introduces longer propagation delays. Segmented routing channels reduce the need for programmable interconnect, but buffers are necessary to drive signals, adding to circuit area. In addition, for signals that travel a long distance, delay can be significant. By going to a 3D design that allows flexible interconnect in every dimension, we expect to relieve routing congestion and shorten interconnect lengths dramatically, thus improving speed. An FPGA's speed is a measure of the delay required to implement a function and to propagate signals to neighboring functions. FPGA logic is often slow due to interconnect delay, which can account for over 70% of the clock cycle period. Another problem with FPGA designs is the number of I/O connections available. According to Rent's rule, the number of I/O pins needed on an FPGA grows faster than the square root of the number of logic elements. However, the number of perimeter bonding pads that can fit along the die periphery only grows as the square root of the area. This means that for a given pad pitch (about 100 microns) and logic element pitch, there is a die size beyond which the demand for I/O far exceeds the supply. In that case, the device becomes pin-limited. Experience with existing FPGAs shows that this results in low logic element utilization. Researchers have proposed using multichip modules (MCMs), area I/O, and optical interconnections to address some of these issues. 1-4 These technologies all require that

Performance benefits of monolithically stacked 3D-FPGA

“…For example, in [15], a 3-D FPGA built by stacking several 2-D FPGA bare dies and vertically connecting their pads using solder bumps is proposed. Inspired by the 2-D Triptych architecture [16], the work in [17] describes the Rothko 3-D architecture [17] in which routing-andLBs are envisioned to be placed on multiple layers and interconnected using the wafer-stacking technology described in [18]. In [19], placement and routing for a 3-D FPGA using the wafer-stacking approach is investigated.…”

Exploring Potential Benefits of 3D FPGA Integration

“…The placement algorithm is partitioning-based and has integrated techniques for minimization 5 We should emphasize, however, that this bound is not going to be far off from a post-routing analysis. In the 2D FPGA architectures of today, the delay of longer segments is comparable to the delay of unit segments.…”

“…This setup serves the purpose of analyzing the upper bound of maximum potential delay improvements using our method, which can be achieved by the 3D integration 5 . The simulation results are shown in Fig.…”

“…Depreitere et al proposed using optical interconnects to construct a multi-layer FPGA [2]. An straightforward extension of a 2D architecture [6] is found in the Rothko 3D architecture, which has routing-and-logic blocks (RLBs) placed in more than one layer [5]. Fine-grained interlayer connections were added outside each RLB, providing connections between cells above and below, using a specially designed technique [8], [9].…”

Three dimensional system on chip technology

“…Some results have appeared in the literature discussing three-dimensional (3-D) circuits and architectures: some focus on the creation of 3-D logic gates and building blocks, while others examine the possibility of creating more complex circuits and architectures [7][8][9][10][11][12].…”