Three dimensional system on chip technology

Abstract

With ever-finer device geometry, increasing device counts and interconnect delays playing a larger role in the performance of a system on a chip, the architectures that are used to support such technologies must take these factors into account. Highly pipelined or highly parallel architectures that utilize local processing, and therefore shorter interconnects, are required.Three-dimensional, monolithic integrated circuit technology which can significantly shorten the interconnects and accommodate more devices per chip may be an attractive solution. The basic idea is presented along with an illustrative application specific processor design.

Systolic FFT Processors: A Personal Perspective

“…A potential solution is to develop two chips (one with the logic circuits and one with the dynamic RAM) and physically stack the chips with the smaller one (probably the dynamic RAM) on top of the larger chip. See [11] for more details on the notion of Bstacked SOC^technology. …”