The evolution of surface roughening during etching of TaN, TiN, Si, HfN, and IrO 2 in Cl 2 was studied. It was observed that surface roughness depended on self-bias voltage and pressure; lower surface roughness was obtained at higher bias voltage and lower pressure during etching of TaN, TiN, and Si in Cl 2 whose boiling temperature of by-products is low, whereas the lower surface roughness was obtained at lower bias voltage and higher pressure during etching of HfN and IrO 2 in Cl 2 whose boiling temperature of by-products is high. It was understood that the contrasting trends from the experimental results originate from the different volatility of the etch by-products which were generated during etching in Cl 2 . It was also observed that, when bias voltage and pressure varied, surface roughness was inversely proportional to etch rate during etching of TaN, TiN, and Si, while surface roughness was proportional to etch rate of HfN and IrO 2 in Cl 2 . In addition, it was found that surface roughness increased as a function of etching time and the effect of etching time on surface roughness was more conspicuous during etching of HfN and IrO 2 .Plasma etching has been widely used to fabricate nanoelectronic devices such as integrated circuits, microelectromechanical system ͑MEMS͒ devices, and photonic devices. It plays a crucial role in current and future device performance. As new gate materials are introduced in complementary metal oxide semiconductor ͑CMOS͒ technology and device dimensions continue to shrink, surface properties induced by nonvolatile etch by-products become critical. In the CMOS technology, for example, new gate stacks consisting of metal electrodes/high dielectric constant ͑k͒ materials have been introduced to replace conventional poly-Si/SiO 2 . During plasma etching of the metal electrode/high-k gate stack, more nonvolatile byproducts were generated on the active area and a more roughened surface resulted, compared to the conventional poly-Si/SiO 2 gate stack. This surface roughening induced by nonvolatile by-products becomes more conspicuous, thereby affecting the device performance more sensitively, as device dimensions continue to be scaled down. 1,2 For instance during gate-stack etching of the metal electrode/high-k dielectric, the etched surface of metal-gate electrode is transferred to the underlying high-k dielectric. In turn, it leads to nonuniform over/etching of source/drain ͑S/D͒ regions; shallow S/Ds can be easily degraded.Evolution mechanisms on surface topography of silicon have been studied previously, motivated by concerns on device performance. 3-6 Petri et al. conducted a parametric study on surface roughening during single-crystal silicon etching by SF 6 plasma using atomic force microscopy ͑AFM͒. 3 They investigated the relations between the ratio of the ion flux over the reactive neutral flux ͑J i /J n ͒ and the surface roughness under various plasma conditions. Zhao et al. also performed a quantitative analysis on topography of the etched surface of Si͑100͒ to examine t...