Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

Abstract

In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) networkon-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems.TDM inherently requires a common time reference, and existing TDM-based NOC designs are either synchronous or mesochronous, but both approaches have their limitations: a globally synchronous NOC is no longer feasible in today's submicron technologies and a mesochronous NOC requires special FIFO-based synchronizers in all input ports of all routers in order to accommodate for clock phase differences. This adds hardware complexity and increases area and power consumption.We propose to use asynchronous routers in order to achieve a simpler, more robust and globally-asynchronous NOC, and this represents an unexplored point in the design space.The paper presents a range of alternative router designs. All routers have been synthesized for a 65 nm CMOS technology, and the paper reports post-layout figures for area, speed and energy and compares the asynchronous designs with an existing mesochronous clocked router. The results show that an asynchronous router is 2 times smaller, marginally slower and with roughly the same energy consumption, while offering a robust solution to the clock distribution problem. The paper further explores "clock-gating" of the individual pipeline stages in the asynchronous routers, and shows that this can lead to significant power savings.

Models of Communication for Multicore Processors

“…Early examples of TDM based NoC's are Nostrum [31] and AEtheral/aelite [32] that is used in the CompSoC multiprocessor platform [33]. More recently we have developed the Argo NoC [34], [35], [36], [37]. Argo has a very efficient implementation due to the use of asynchronous routers and a novel NI architecture.…”

T-CREST: Time-predictable multi-core architecture for embedded systems

“…Examples are controllers in airplanes, braking controllers in cars, or train control systems. Those safetycritical systems need to be certified and the maximum execution time needs 5 to be bounded and known so that response times can be assured when critical situations require a timely reaction. Note that just using a faster processor is not a solution for time predictability.…”

“…This is traditionally provided 610 by adding dual-clock FIFOs in every input port of every router as illustrated in Figure 3. The addition of these FIFOs roughly doubles the area and power consumption of a clocked synchronous router [5]. Our NoC uses asynchronous routers instead and as asynchronous pipelines inherently behave as self-timed ripple FIFOs we avoid these explicit synchronizer FIFOs.…”

“…The handshake latch used in our design consists of a normal enable latch and a 620 handshake controller that implements a two-phase (NRZ) bundled-data protocol [102]. We present the asynchronous router design in more detail in [5]. Figure 6 shows the packet format used in our architecture.…”

Message Passing on a Time-predictable Multicore Processor

“…The T-CREST project [3] developed a time-predictable multicore processor, consisting of the time-predictable processor Patmos [4], a time-predictable memory NoC [5], [6], a timepredictable memory controller [7], [8], and the time-predictable message passing NoC Argo [9], [10]. This paper mainly addresses the software layer for Argo.…”