Routing-aware placement algorithms for modern analog integrated circuits

Lin, Cheng-Wu; Lu, Cheng-Chung; Huang, Chun-Po; Chang, Soon-Jyh; Lin, Jai-Ming

doi:10.1109/mwscas.2011.6026537

“…Instead of applying the naive routing method in many of the previous works, such as [7,10,11,12,16], or adopting the complex routing method [5], we present a simple yet effective approach to generate common-centroid routing. The routing styles generated by the presented approach will help the succeeding step to minimize unit capacitor size while matching C T B i and C T S , which will be detailed in Section 4.3.…”

Section: Common-centroid Detailed Routingmentioning

confidence: 99%

“…Although layout synthesis techniques for ratioed capacitors had been extensively studied, most of the previous works [2,7,8,9,10,11,13,16,17] only emphasized how to generate highly matched common-centroid and/or dispersive placements for ratioed capacitors to minimize the impact from random and systematic mismatch. They failed to consider the routing-induced parasitics which may destroy the resulting matching properties of ratioed capacitors even if the placement is perfectly matched.…”

Section: Introductionmentioning

confidence: 99%

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC

Hsiao

¹

,

Lin

²

2014

Proceedings of the 51st Annual Design Automation Conference

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Capacitor sizing is a crucial step when designing a chargescaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state of the art.

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“…Instead of applying the naive routing method in many of the previous works, such as [7,10,11,12,16], or adopting the complex routing method [5], we present a simple yet effective approach to generate common-centroid routing. The routing styles generated by the presented approach will help the succeeding step to minimize unit capacitor size while matching C T B i and C T S , which will be detailed in Section 4.3.…”

Section: Common-centroid Detailed Routingmentioning

confidence: 99%

Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling DAC

Hsiao¹,

Lin²

2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

9

0

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Capacitor sizing is a crucial step when designing a chargescaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state of the art.

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Automatic placement for matched devices of analog circuits

Wu

¹

,

Zhang

²

,

Chen

³

et al. 2013

2013 Ninth International Conference on Natural Computation (ICNC)

1

0

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It is time-consuming to obtain the matched devices by manual analysis and place them in hand for analog circuits of the mixed signal system. To achieve high performance, matched placement is a key point to layout design of analog circuits. In order to simplify layout design, it is necessary to realize the procedure automatically. In this paper, a method for automatic analog circuit placement is provided, as well as an efficient algorithm for the matched device groups. The experimental results verify the automatic placement algorithm of matched device groups.

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Routing-aware placement algorithms for modern analog integrated circuits

Cited by 8 publications

References 15 publications

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC

Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling DAC

Automatic placement for matched devices of analog circuits

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