Row-buffer hit harvesting in orchestrated last-level cache and DRAM scheduling for heterogeneous multicore systems

Song, Yang; Alavoine, Olivier; Lin, Bill

doi:10.23919/date.2018.8342112

Cited by 3 publications

(3 citation statements)

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“…Locality dilution can be tackled in two ways: (1) increase memory visibility and make more requests visible to the scheduler so that the dilution can be tolerated and (2) preserve memory locality and prevent requests for the same row from being dispersed. The first approach has been well explored by previous work [13,16,27,30], whereas the second approach has drawn little attention in recent years [12,24,35]. Figure 4 shows the results from varying memory visibility and locality.…”

Section: Background and Motivationmentioning

confidence: 99%

“…Eager writebacks are triggered by row activations regardless of the cause. Recently a unified memory controller [27] was proposed to orchestrate cache request arbiter with memory scheduler so that potential row-buffer hits can be harvested during cache request arbitration.…”

Section: Related Workmentioning

confidence: 99%

“…Besides memory scheduling policies, prior work have also explored improving memory visibility for the scheduler so that more row-buffer hit opportunities can be revealed. Several cache replacement and eviction policies in consideration of row-buffer states [13,16,27,30] have been proposed for CPU-centric homogeneous systems. These work extend the candidate pool for memory scheduling into caches to provide more visibility of memory traffic to the scheduler.…”

Section: Introductionmentioning

confidence: 99%

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Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding

Song

Lin

2020

ACM Trans. Archit. Code Optim.

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In heterogeneous multicore systems, the memory subsystem plays a critical role, since most core-to-core communications are conducted through the main memory. Memory efficiency has a substantial impact on system performance. Although memory traffic from multimedia cores generally manifests high row-buffer locality, which is beneficial to memory efficiency, the locality is often lost as memory streams are forwarded through networks-on-chip (NoC). Previous studies have discussed the techniques that improve memory visibility to reveal scattered row-buffer hit opportunities to the memory scheduler. However, extending local memory visibility introduces little benefit after the locality has been severely diluted. As the alternative approach, preserving row-buffer locality in the NoC has not been well explored. What is worse, it remains to be studied how to perform network traffic scheduling with the awareness of both memory efficiency and quality-of-service (QoS). In this article, we propose a router design with embedded row-index caches to enable locality-aware packet forwarding. The proposed design requires minor modifications to existing router microarchitecture and can be easily implemented with priority arbiters to integrate QoS support. Extensive evaluations show that the proposed design achieves higher memory efficiency than prior memory-aware routers, in addition to providing QoS support. On basis of extant QoS-aware routers, locality-aware forwarding helps to increase row-buffer hits by 58.32% and reduce memory latency by 14.45% on average. It also introduces a net reduction in DRAM and NoC energy cost by 27.82%.

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Section: Background and Motivationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding

Song

Lin

2020

ACM Trans. Archit. Code Optim.

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Real

Tiwari

Tuli

Ahmad

et al. 2019

ACM Trans. Embed. Comput. Syst.

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Shared last level caches (LLC) of multicore systems-on-chip are subject to a significant amount of contention over a limited bandwidth, resulting in major performance bottlenecks that make the issue a first-order concern in modern multiprocessor systems-on-chip. Even though shared cache space partitioning has been extensively studied in the past, the problem of cache bandwidth partitioning has not received sufficient attention. We demonstrate the occurrence of such contention and the resulting impact on the overall system performance. To address the issue, we perform detailed simulations to study the impact of different parameters and propose a novel cache bandwidth partitioning technique, called REAL , that arbitrates among cache access requests originating from different processor cores. It monitors the LLC access patterns to dynamically assign a priority value to each core. Experimental results on different mixes of benchmarks show up to 2.13× overall system speedup over baseline policies, with minimal impact on energy.

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CABARRE: Request Response Arbitration for Shared Cache Management

Modi,

Bagchi,

Jindal

et al. 2023

ACM Trans. Embed. Comput. Syst.

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Modern multi-processor systems-on-chip (MPSoCs) are characterized by caches shared by multiple cores. These shared caches receive requests issued by the processor cores. Requests that are subject to cache misses may result in the generation of responses . These responses are received from the lower level of the memory hierarchy and written to the cache. The outstanding requests and responses contend for the shared cache bandwidth. To mitigate the impact of the cache bandwidth contention on the overall system performance, an efficient request and response arbitration policy is needed. Research on shared cache management has neglected the additional cache contention caused by responses, which are written to the cache. We propose CABARRE , a novel request and response arbitration policy at shared caches, so as to improve the overall system performance. CABARRE shows a performance improvement of 23% on average across a set of SPEC workloads compared to straightforward adaptations of state-of-the-art solutions.

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Row-buffer hit harvesting in orchestrated last-level cache and DRAM scheduling for heterogeneous multicore systems

Cited by 3 publications

References 9 publications

Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding

Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding

Real

CABARRE: Request Response Arbitration for Shared Cache Management

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