RPPM: Rapid Performance Prediction of Multithreaded Workloads on Multicore Processors

Pestel, Sander De; Steen, Sam Van den; Akram, Shoaib; Eeckhout, Lieven

doi:10.1109/ispass.2019.00038

Cited by 6 publications

(3 citation statements)

References 43 publications

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“…Eyerman et al [42] proposed a model to divide the dynamic instruction stream into long-latency miss events that limit the scope of out-of-order behaviors. RPPM [43] takes into account synchronization overheads by identifying critical paths to project multithreaded performance. Statstack [44] and Linear branch entropy [45] are proposed to model the cache miss ratio of a fully associative cache and the branch miss rate of any branch predictor, respectively.…”

Section: Analytical Modelingmentioning

confidence: 99%

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Sabu,

Liu,

Carlson

2024

IEEE Access

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Pre-silicon performance evaluation is a crucial component of computer systems research and development. While simulation has long been the de facto standard in this context, it can be prohibitively time-consuming for long-running, realistic workloads. To expedite this process, researchers have traditionally turned to sampling techniques. However, these techniques typically rely on fixed-length intervals for analysis, which can often be out of sync with the periodicity of program execution. Additionally, since an application's phase behavior is strongly correlated to the code it executes, it can exhibit a hierarchy of phase behaviors that can be observed at various interval lengths, rendering conventional sampling techniques inadequate. To address these limitations, we propose Viper -a novel sampled simulation methodology that applies to single-threaded and multi-threaded workloads by leveraging the hierarchical structure of program execution. Viper takes into account both application periodicity and inter-thread synchronization in order to achieve better sampling accuracy and smaller regions, which enables faster register-transfer level (RTL) simulations. We evaluate Viper with the multi-threaded SPEC CPU2017 benchmarks and demonstrate a significant simulation speedup (up to 2,710×, 358× on average for the train input set) while maintaining an average sampling error of just 1.32%.

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Section: Analytical Modelingmentioning

confidence: 99%

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Sabu,

Liu,

Carlson

2024

IEEE Access

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“…Machine learning (e.g., neural networks [9] and splinebased regression [10]) was previously proposed to explore single-core and multi-core design spaces, however, predicting performance for larger-scale target systems fell out of reach for these models. Analytical models have been proposed for multi-core processors for both multiprogram workloads [11], [12] and multi-threaded workloads [13]. An inherent challenge for such models is how to analytically model overlap effects as well as timing-sensitive events in large target systems; scalemodel simulation addresses this challenge through extrapolation.…”

Section: Related Workmentioning

confidence: 99%

Scale-Model Architectural Simulation

Liu

Heirman²,

Eyerman³

et al. 2022

2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Computer architects extensively use simulation to steer future processor research and development. Simulating large-scale multicore processors is extremely time-consuming and is sometimes impossible because of simulation infrastructure constraints and/or simulation host compute and memory limitations.This paper proposes scale-model simulation, a novel methodology to predict large-scale multicore system performance. Scalemodel simulation first constructs and simulates a scale model of the target system with reduced core count and shared resources. Target system performance is then predicted through machinelearning (ML) based extrapolation. Scale-model simulation predicts 32-core target system performance based on a singlecore scale model with an average error of 8.0% and 15.8% for homogeneous and heterogeneous multiprogram workloads, respectively, while yielding a 28× simulation speedup.

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“…Abstract system-level simulators have long been used in the architecture and design automation communities for performance estimation and analysis [11,19,27,38,39,42,44,49,52]. In particular, [12] used system simulation to evaluate the interaction between the OS and a 10 Gbit/s Ethernet NIC.…”

Section: Related Workmentioning

confidence: 99%

FirePerf

Karandikar

Amid

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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Achieving high-performance when developing specialized hardware/software systems requires understanding and improving not only core compute kernels, but also intricate and elusive system-level bottlenecks. Profiling these bottlenecks requires both high-fidelity introspection and the ability to run sufficiently many cycles to execute complex software stacks, a challenging combination. In this work, we enable agile full-system performance optimization for hardware/ software systems with FirePerf, a set of novel out-of-band system-level performance profiling capabilities integrated into the open-source FireSim FPGA-accelerated hardware simulation platform. Using out-of-band call stack reconstruction and automatic performance counter insertion, FirePerf enables introspecting into hardware and software at appropriate abstraction levels to rapidly identify opportunities for software optimization and hardware specialization, without disrupting end-to-end system behavior like traditional profiling tools. We demonstrate the capabilities of FirePerf with a case study that optimizes the hardware/software stack of an open-source RISC-V SoC with an Ethernet NIC to achieve 8× end-to-end improvement in achievable bandwidth for networking applications running on Linux. We also deploy a RISC-V Linux kernel optimization discovered with FirePerf on commercial RISC-V silicon, resulting in up to 1.72× improvement in network performance.

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RPPM: Rapid Performance Prediction of Multithreaded Workloads on Multicore Processors

Cited by 6 publications

References 43 publications

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Scale-Model Architectural Simulation

FirePerf

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