RS flip‐flop implementation based on all spin logic devices

Wang, Sen; Cai, Li; Feng, Chaowen; Cui, Huanqing; Yang, Xiaokuo; Zhao, Hongyan

doi:10.1049/mnl.2016.0589

Cited by 9 publications

(7 citation statements)

References 20 publications

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“…One is the asymmetric ground leads position that guarantees the flowing direction of information from input to output in ASL devices [9]. The other is the complementary clock signal scheme that controls the transmitting of signals [14].…”

Section: Xor Gate Designmentioning

confidence: 99%

“…Especially, all-spin logic (ASL) device does not need extra hardware to implementing spin-to-charge conversion repeatedly, because spin is used at every stage of information processing, transfer, and storage [7]. Thus, ASL device has been proposed as a potential beyond-CMOS option for future digital logic application [8] and has attracted wide attention [9][10][11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

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All‐spin logic XOR gate implementation based on input interface

Wang

Yang

Song

et al. 2019

IET Circuits, Devices & Systems

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An input interface for all-spin logic (ASL) circuits is proposed, which is composed of magnetic tunnel junction (MJT) and metal wires that are used for transmitting electrical signals. The proposed input interface can shorten the length of nonmagnetic channel and avoid the complex fan-out structure, and is fit for the circuits that need multiple same input signals. Moreover, based on the ASL minority gate and inverter, two kinds of XOR gates are designed. Compared with the XOR gate without input interface, the XOR gate using input interface possesses lower energy dissipation and higher reliability. Using coupled spin-transport/magneto-dynamics models, validity of the input interface and XOR gates are demonstrated. This work provides an interesting approach for the design of large-scale ASL circuits that contain many identical input ports.

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Section: Xor Gate Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

All‐spin logic XOR gate implementation based on input interface

Wang

Yang

Song

et al. 2019

IET Circuits, Devices & Systems

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show abstract

“…In particular, ASL does not require additional hardware for repeated spin-charge conversion, which has attracted considerable attention [11][12][13][14][15][16][17][18]. Various types of logic circuits based on ASL have been proposed, such as full adder [19], D flip-flop [20], RS flip-flop [21], and XOR gate [22]. However, as an important element in logic circuits, the decoder has not been reported in the public as much as we know.…”

Section: Introductionmentioning

confidence: 99%

Proposal of a 2-4 Decoder Based on All-spin Logic and Magnetic Tunnel Junction

Wang,

Zhang,

Shan

2024

Preprint

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A 2–4 decoder based on all-spin logic (ASL) and magnetic tunnel junction (MTJ) is proposed. The proposed 2–4 decoder employs 5-input minority gates and single-input single-fan-out (SISF) structure. Meanwhile, the inverters are eliminated by initializing the magnetization of the MTJ fixed layer in different directions to realize the inputs of the original or inverse variables. To ensure that the proposed 2–4 decoder works properly, an asynchronous clock scheme is proposed, which divides the input signal into three phases and the operating voltage into two phases in one clock cycle. The operation of the proposed decoder is validated by the magnetization dynamics/spin transport self-consistent simulation framework, and the simulation results show that the delay and energy dissipation of the decoder are at the level of nanosecond and femtojoule, respectively. In addition, to illustrate the advantages of the 5-input minority gate, inverter-free structure, and SISF structures in the design of the proposed 2–4 decoder, a second 2–4 decoder is proposed using 3-input minority gates, inverters, and single-input multiple-fan-out structure. Compared with the second decoder, the layout area of the first decoder is reduced to 37.9%, the total channel length is reduced to 40.8%, the number of clock cycles is reduced to 1/3, and the energy dissipation is reduced by at least 3 orders of magnitude. Importantly, the design methods used in this work, such as multi-input minority gates, SISF structure, and inverter-free structure, provide an interesting approach for designing large-scale ASL logic circuits.

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“…But, fortunately, ASLD does not need extra hardware for implementing spin-charge conversion repeatedly, because spin is used at every stage of information processing, transfer, and storage [8]. Thus, ASLD is relatively simpler than other spintronic devices in structure and has been widely studied in the aspects of device switching mechanism [9][10][11], material and structural optimization [12][13][14][15][16][17][18][19][20][21][22][23], and circuit design [24][25][26].…”

Section: Introductionmentioning

confidence: 99%

Proposal for a spin logic device based on magneto‐electric effect and spin Hall effect

Wang

Zhang

et al. 2023

Micro & Nano Letters

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Based on magneto-electric (ME) effect and spin Hall effect (SHE), the authors propose a novel spin logic device named MESH-SLD. In MESH-SLD, the charge current is transmitted in the channel by employing inverse SHE, which solves the dissipation problem of spin current in the channel of all-spin logic device (ASLD). By using a magnetizationdynamics/spin-transport hybrid model, the authors have investigated the influence of working voltage, channel lengths, and materials on the performance of the MESH-SLD. And the simulation results show that the energy dissipation of the MESH-SLD only increases approximately linearly with the increase of channel length, while the switching delay remains almost unchanged. In addition, with the increase of the spin Hall angle of the channel material, the energy dissipation and the minimum working voltage of the MESH-SLD decrease significantly. Most importantly, compared with conventional ASLD, the proposed MESH-SLD improve the switching delay and the energy dissipation by about 2.5 times and 851.8 times, respectively.

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RS flip‐flop implementation based on all spin logic devices

Cited by 9 publications

References 20 publications

All‐spin logic XOR gate implementation based on input interface

All‐spin logic XOR gate implementation based on input interface

Proposal of a 2-4 Decoder Based on All-spin Logic and Magnetic Tunnel Junction

Proposal for a spin logic device based on magneto‐electric effect and spin Hall effect

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