Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams

Amla, Nina; Kurshan, Robert P.; Namjoshi, Kedar S.

doi:10.1007/3-540-44585-4_38

Cited by 5 publications

(2 citation statements)

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“…In a second approach, Amla et al [1999Amla et al [ , 2001 defined Regular Timing Diagrams (RTDs), a class of timing diagrams for which both a precise semantics and a decompositional model-checking algorithm exist. The language includes mechanisms for iterating and overlapping the execution of the specification diagrams.…”

Section: Timing Diagramsmentioning

confidence: 99%

“…First, their formal semantics makes specifications precise. Second, their usage as specification languages [Amla et al 2000[Amla et al , 2001 as well as that of their successor language, Modular Timing Diagrams [Amla et al 2002], comes directly from the verification tool community, and so many tools and automatic verification techniques can be leveraged. Finally, since timing diagrams are commonly used as design teaching tools, they are already fully integrated into industrial design and verification practice.…”

Section: Timing Diagramsmentioning

confidence: 99%

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Formal hardware specification languages for protocol compliance verification

Bunker

Gopalakrishnan

McKee

2004

ACM Trans. Des. Autom. Electron. Syst.

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The advent of the system-on-chip and intellectual property hardware design paradigms makes protocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally intended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the development of the language, an evaluation of the language's utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered.

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Section: Timing Diagramsmentioning

confidence: 99%

Section: Timing Diagramsmentioning

confidence: 99%

Formal hardware specification languages for protocol compliance verification

Bunker

Gopalakrishnan

McKee

2004

ACM Trans. Des. Autom. Electron. Syst.

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Visual Specifications for Modular Reasoning about Asynchronous Systems

Amla

Namjoshi

Trefler

2002

Formal Techniques for Networked and Distributed Sytems — FORTE 2002

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Abstract. We propose a framework that closely ties together visual specification and modular reasoning of asynchronous systems. The basis of the framework is a new notation, called Modular Timing Diagrams (MTD's), for specifying the universal properties about causality and timing of events in an asynchronous system. MTD's are complementary in nature to Message Sequence Charts, that are typically used to specify existential properties. Our framework includes two algorithms for formal reasoning with MTD's. The first is an efficient polynomial-time model checking algorithm. The second is an algorithm for automatically generating an assume-guarantee partitioning of an MTD, that exploits its inherent decompositional structure. We show how to use this decomposition for modular reasoning with MTD properties in conjunction with an asynchronous compositional reasoning rule. To illustrate the notation and our method, we describe a case study where we specified telephony features, such as call forwarding with MTD's, and verified these properties on an asynchronous telephony model. The compositional reasoning methods led to savings of 15%-80% in verification times, and comparable savings in space.

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